Implementation sources

osfmk/arm64/proc_reg.h

xnu source @ f6217f8 2025-10-16 · 3617 lines · view on GitHub
1/* 2 * Copyright (c) 2007-2024 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28/* 29 * @OSF_COPYRIGHT@ 30 */ 31/* CMU_ENDHIST */ 32/* 33 * Mach Operating System 34 * Copyright (c) 1991,1990 Carnegie Mellon University 35 * All Rights Reserved. 36 * 37 * Permission to use, copy, modify and distribute this software and its 38 * documentation is hereby granted, provided that both the copyright 39 * notice and this permission notice appear in all copies of the 40 * software, derivative works or modified versions, and any portions 41 * thereof, and that both notices appear in supporting documentation. 42 * 43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * Carnegie Mellon requests users of this software to return to 48 * 49 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 50 * School of Computer Science 51 * Carnegie Mellon University 52 * Pittsburgh PA 15213-3890 53 * 54 * any improvements or extensions that they make and grant Carnegie Mellon 55 * the rights to redistribute these changes. 56 */ 57 58/* 59 * Processor registers for ARM/ARM64 60 */ 61#ifndef _ARM64_PROC_REG_H_ 62#define _ARM64_PROC_REG_H_ 63 64#if !defined(KERNEL_PRIVATE) && !defined(SPTM_TESTING_PRIVATE) 65/** 66 * This file is only exported into the internal userspace SDK exclusively for 67 * usage by the SPTM userspace testing system. Let's enforce this by error'ing 68 * the build if an SPTM-specific define is not set. If your userspace project is 69 * not the SPTM testing system, then do not use these files! 70 * 71 * This check does not apply to the kernel itself, or when this file is exported 72 * into Kernel.framework. 73 */ 74#error This file is only included in the userspace internal SDK for the SPTM project 75#endif /* !defined(KERNEL_PRIVATE) && !defined(SPTM_TESTING_PRIVATE) */ 76 77#if defined (__arm64__) 78#include <pexpert/arm64/board_config.h> 79#elif defined (__arm__) 80#include <pexpert/arm/board_config.h> 81#endif 82 83#if !CONFIG_SPTM 84/* 85 * Processor registers for ARM 86 */ 87#if __ARM_42BIT_PA_SPACE__ 88/** 89 * On PPL, the identity map requires a smaller T0SZ value because DRAM starts 90 * at a PA not mappable by only 3 bits in L1 table on platforms with 42-bit 91 * PA space. On SPTM, this is overcome by boot with a smaller T0SZ and resize 92 * to the __ARM64_PMAP_SUBPAGE_L1__ T0SZ when the identity map is no longer 93 * used. 94 */ 95#undef __ARM64_PMAP_SUBPAGE_L1__ 96#undef __ARM64_PMAP_KERN_SUBPAGE_L1__ 97#endif /* __ARM_42BIT_PA_SPACE__ */ 98#endif /* !CONFIG_SPTM */ 99 100/* For arm platforms, create one pset per cluster */ 101#define MAX_PSETS MAX_CPU_CLUSTERS 102 103 104/* Thread groups are enabled on all ARM platforms (irrespective of scheduler) */ 105#define CONFIG_THREAD_GROUPS 1 106 107#ifdef XNU_KERNEL_PRIVATE 108 109#if __ARM_VFP__ 110#define ARM_VFP_DEBUG 0 111#endif /* __ARM_VFP__ */ 112 113#endif /* XNU_KERNEL_PRIVATE */ 114 115/* 116 * FSR registers 117 * 118 * CPSR: Current Program Status Register 119 * SPSR: Saved Program Status Registers 120 * 121 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0 122 * +-----------------------------------------------------------+ 123 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE | 124 * +-----------------------------------------------------------+ 125 */ 126 127/* 128 * Flags 129 */ 130#define PSR_NF 0x80000000 /* Negative/Less than */ 131#define PSR_ZF 0x40000000 /* Zero */ 132#define PSR_CF 0x20000000 /* Carry/Borrow/Extend */ 133#define PSR_VF 0x10000000 /* Overflow */ 134 135/* 136 * Modified execution mode flags 137 */ 138#define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */ 139 140/* 141 * CPU mode 142 */ 143#define PSR_USER_MODE 0x00000010 /* User mode */ 144 145#define PSR_MODE_MASK 0x0000001F 146#define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE) 147#define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE) 148 149#define PSR_USERDFLT PSR_USER_MODE 150 151#define PSR_BTYPE_SHIFT (10) 152#define PSR_BTYPE_MASK (0x3 << PSR_BTYPE_SHIFT) 153 154/* 155 * Cache configuration 156 */ 157 158#if defined (APPLETYPHOON) 159 160/* I-Cache */ 161#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 162 163/* D-Cache */ 164#define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ 165 166#elif defined (APPLETWISTER) 167 168/* I-Cache */ 169#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 170 171/* D-Cache */ 172#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 173 174#elif defined (APPLEHURRICANE) 175 176/* I-Cache */ 177#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 178 179/* D-Cache */ 180#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 181 182#elif defined (APPLEMONSOON) 183 184/* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */ 185#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 186 187/* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */ 188#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 189 190#elif defined (APPLEVORTEX) 191 192/* I-Cache, 128KB 8-way for Vortex, 48KB 6-way for Tempest. */ 193#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 194 195/* D-Cache, 128KB 8-way for Vortex, 32KB 4-way for Tempest. */ 196#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 197 198#elif defined (APPLELIGHTNING) 199 200/* I-Cache, 192KB for Lightning, 96KB for Thunder, 6-way. */ 201#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 202 203/* D-Cache, 128KB for Lightning, 8-way. 48KB for Thunder, 6-way. */ 204#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 205 206#elif defined (APPLEFIRESTORM) 207 208/* I-Cache, 256KB for Firestorm, 128KB for Icestorm, 6-way. */ 209#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 210 211/* D-Cache, 160KB for Firestorm, 8-way. 64KB for Icestorm, 6-way. */ 212#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 213 214#elif defined (APPLEAVALANCHE) 215 216/* I-Cache, 192KB for Avalanche, 128KB for Blizzard, 6-way. */ 217#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 218 219/* D-Cache, 128KB for Avalanche, 8-way. 64KB for Blizzard, 8-way. */ 220#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 221 222#elif defined (APPLEEVEREST) 223 224/* I-Cache, 192KB for Everest, 128KB for SawTooth, 6-way. */ 225#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 226 227/* D-Cache, 128KB for Everest, 8-way. 64KB for SawTooth, 8-way. */ 228#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 229 230#elif defined (APPLEH16) 231 232/* I-Cache, 192KB for AppleH16 PCore, 128KB for ECore, 6-way. */ 233#define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 234 235/* D-Cache, 128KB for AppleH16 PCore, 8-way. 64KB for ECore, 8-way. */ 236#define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 237 238#elif defined (VMAPPLE) 239 240/* I-Cache. */ 241#define MMU_I_CLINE 6 242 243/* D-Cache. */ 244#define MMU_CLINE 6 245 246#else 247#error processor not supported 248#endif 249 250#define MAX_L2_CLINE_BYTES (1 << MAX_L2_CLINE) 251 252/* 253 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers 254 */ 255#define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */ 256#define ARM_DBG_VR_ADDRESS_MASK64 0xFFFFFFFFFFFFFFFCull /* BVR & WVR */ 257 258#define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */ 259#define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */ 260#define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */ 261#define ARM_DBGBCR_TYPE_IVA (0 << 21) 262#define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */ 263#define ARM_DBG_CR_LINKED_UNLINKED (0 << 20) 264#define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14) 265#define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13) 266#define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */ 267#define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */ 268#define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */ 269#define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */ 270#define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */ 271#define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */ 272#define ARM_DBG_CR_ENABLE_ENABLE (1 << 0) 273 274/* 275 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR) 276 */ 277#define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55 278 279/* ARM Debug registers of interest */ 280#define ARM_DEBUG_OFFSET_DBGPRCR (0x310) 281#define ARM_DEBUG_OFFSET_DBGLAR (0xFB0) 282 283/* 284 * Main ID Register (MIDR) 285 * 286 * 31 24 23 20 19 16 15 4 3 0 287 * +-----+-----+------+------+-----+ 288 * | IMP | VAR | ARCH | PNUM | REV | 289 * +-----+-----+------+------+-----+ 290 * 291 * where: 292 * IMP: Implementor code 293 * VAR: Variant number 294 * ARCH: Architecture code 295 * PNUM: Primary part number 296 * REV: Minor revision number 297 */ 298#define MIDR_REV_SHIFT 0 299#define MIDR_REV_MASK (0xf << MIDR_REV_SHIFT) 300#define MIDR_VAR_SHIFT 20 301#define MIDR_VAR_MASK (0xf << MIDR_VAR_SHIFT) 302 303 304#if __ARM_KERNEL_PROTECT__ 305/* 306 * __ARM_KERNEL_PROTECT__ is a feature intended to guard against potential 307 * architectural or microarchitectural vulnerabilities that could allow cores to 308 * read/access EL1-only mappings while in EL0 mode. This is achieved by 309 * removing as many mappings as possible when the core transitions to EL0 mode 310 * from EL1 mode, and restoring those mappings when the core transitions to EL1 311 * mode from EL0 mode. 312 * 313 * At the moment, this is achieved through use of ASIDs and TCR_EL1. TCR_EL1 is 314 * used to map and unmap the ordinary kernel mappings, by contracting and 315 * expanding translation zone size for TTBR1 when exiting and entering EL1, 316 * respectively: 317 * 318 * Kernel EL0 Mappings: TTBR1 mappings that must remain mapped while the core is 319 * is in EL0. 320 * Kernel EL1 Mappings: TTBR1 mappings that must be mapped while the core is in 321 * EL1. 322 * 323 * T1SZ_USER: T1SZ_BOOT + 1 324 * TTBR1_EL1_BASE_BOOT: (2^64) - (2^(64 - T1SZ_BOOT) 325 * TTBR1_EL1_BASE_USER: (2^64) - (2^(64 - T1SZ_USER) 326 * TTBR1_EL1_MAX: (2^64) - 1 327 * 328 * When in EL1, we program TCR_EL1 (specifically, TCR_EL1.T1SZ) to give the 329 * the following TTBR1 layout: 330 * 331 * TTBR1_EL1_BASE_BOOT TTBR1_EL1_BASE_USER TTBR1_EL1_MAX 332 * +---------------------------------------------------------+ 333 * | Kernel EL0 Mappings | Kernel EL1 Mappings | 334 * +---------------------------------------------------------+ 335 * 336 * And when in EL0, we program TCR_EL1 to give the following TTBR1 layout: 337 * 338 * TTBR1_EL1_BASE_USER TTBR1_EL1_MAX 339 * +---------------------------------------------------------+ 340 * | Kernel EL0 Mappings | 341 * +---------------------------------------------------------+ 342 * 343 * With the current implementation, both the EL0 and EL1 mappings for the kernel 344 * use otherwise empty translation tables for mapping the exception vectors (so 345 * that we do not need to TLB flush the exception vector address when switching 346 * between EL0 and EL1). The rationale here is that the TLBI would require a 347 * DSB, and DSBs can be extremely expensive. 348 * 349 * Each pmap is given two ASIDs: (n & ~1) as an EL0 ASID, and (n | 1) as an EL1 350 * ASID. The core switches between ASIDs on EL transitions, so that the TLB 351 * does not need to be fully invalidated on an EL transition. 352 * 353 * Most kernel mappings will be marked non-global in this configuration, as 354 * global mappings would be visible to userspace unless we invalidate them on 355 * eret. 356 */ 357#if XNU_MONITOR 358/* 359 * Please note that because we indirect through the thread register in order to 360 * locate the kernel, and because we unmap most of the kernel, the security 361 * model of the PPL is undermined by __ARM_KERNEL_PROTECT__, as we rely on 362 * kernel controlled data to direct codeflow in the exception vectors. 363 * 364 * If we want to ship XNU_MONITOR paired with __ARM_KERNEL_PROTECT__, we will 365 * need to find a performant solution to this problem. 366 */ 367#endif 368#endif /* __ARM_KERNEL_PROTECT */ 369 370#if ARM_PARAMETERIZED_PMAP 371/* 372 * ARM_PARAMETERIZED_PMAP configures the kernel to get the characteristics of 373 * the page tables (number of levels, size of the root allocation) from the 374 * pmap data structure, rather than treating them as compile-time constants. 375 * This allows the pmap code to dynamically adjust how it deals with page 376 * tables. 377 */ 378#endif /* ARM_PARAMETERIZED_PMAP */ 379 380#if __ARM_MIXED_PAGE_SIZE__ 381/* 382 * __ARM_MIXED_PAGE_SIZE__ configures the kernel to support page tables that do 383 * not use the kernel page size. This is primarily meant to support running 384 * 4KB page processes on a 16KB page kernel. 385 * 386 * This only covers support in the pmap/machine dependent layers. Any support 387 * elsewhere in the kernel must be managed separately. 388 */ 389#if !ARM_PARAMETERIZED_PMAP 390/* 391 * Page tables that use non-kernel page sizes require us to reprogram TCR based 392 * on the page tables we are switching to. This means that the parameterized 393 * pmap support is required. 394 */ 395#error __ARM_MIXED_PAGE_SIZE__ requires ARM_PARAMETERIZED_PMAP 396#endif /* !ARM_PARAMETERIZED_PMAP */ 397#if __ARM_KERNEL_PROTECT__ 398/* 399 * Because switching the page size requires updating TCR based on the pmap, and 400 * __ARM_KERNEL_PROTECT__ relies on TCR being programmed with constants, XNU 401 * does not currently support support configurations that use both 402 * __ARM_KERNEL_PROTECT__ and __ARM_MIXED_PAGE_SIZE__. 403 */ 404#error __ARM_MIXED_PAGE_SIZE__ and __ARM_KERNEL_PROTECT__ are mutually exclusive 405#endif /* __ARM_KERNEL_PROTECT__ */ 406#endif /* __ARM_MIXED_PAGE_SIZE__ */ 407 408/* 409 * 64-bit Program Status Register (PSR64) 410 * 411 * 31 27 23 22 21 20 19 10 9 5 4 0 412 * +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+ 413 * |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0| M | 414 * +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+ 415 * 416 * where: 417 * NZCV: Comparison flags 418 * PAN: Privileged Access Never 419 * SS: Single step 420 * IL: Illegal state 421 * DAIF: Interrupt masks 422 * M: Mode field 423 */ 424 425#define PSR64_NZCV_SHIFT 28 426#define PSR64_NZCV_WIDTH 4 427#define PSR64_NZCV_MASK (0xF << PSR64_NZCV_SHIFT) 428 429#define PSR64_N_SHIFT 31 430#define PSR64_N (1 << PSR64_N_SHIFT) 431 432#define PSR64_Z_SHIFT 30 433#define PSR64_Z (1 << PSR64_Z_SHIFT) 434 435#define PSR64_C_SHIFT 29 436#define PSR64_C (1 << PSR64_C_SHIFT) 437 438#define PSR64_V_SHIFT 28 439#define PSR64_V (1 << PSR64_V_SHIFT) 440 441#define PSR64_TCO_SHIFT 25 442#define PSR64_TCO (1 << PSR64_TCO_SHIFT) 443 444#define PSR64_DIT_SHIFT 24 445#define PSR64_DIT (1 << PSR64_DIT_SHIFT) 446 447#define PSR64_UAO_SHIFT 23 448#define PSR64_UAO (1 << PSR64_UAO_SHIFT) 449 450#define PSR64_PAN_SHIFT 22 451#define PSR64_PAN (1 << PSR64_PAN_SHIFT) 452 453#define PSR64_SS_SHIFT 21 454#define PSR64_SS (1 << PSR64_SS_SHIFT) 455 456#define PSR64_IL_SHIFT 20 457#define PSR64_IL (1 << PSR64_IL_SHIFT) 458 459/* 460 * SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR 461 * I do not want to talk about it! 462 */ 463#define PSR64_SSBS_SHIFT_32 23 464#define PSR64_SSBS_SHIFT_64 12 465#define PSR64_SSBS_32 (1 << PSR64_SSBS_SHIFT_32) 466#define PSR64_SSBS_64 (1 << PSR64_SSBS_SHIFT_64) 467 468/* 469 * msr DAIF, Xn and mrs Xn, DAIF transfer into 470 * and out of bits 9:6 471 */ 472#define DAIF_DEBUG_SHIFT 9 473#define DAIF_DEBUGF (1 << DAIF_DEBUG_SHIFT) 474 475#define DAIF_ASYNC_SHIFT 8 476#define DAIF_ASYNCF (1 << DAIF_ASYNC_SHIFT) 477 478#define DAIF_IRQF_SHIFT 7 479#define DAIF_IRQF (1 << DAIF_IRQF_SHIFT) 480 481#define DAIF_FIQF_SHIFT 6 482#define DAIF_FIQF (1 << DAIF_FIQF_SHIFT) 483 484#define DAIF_ALL (DAIF_DEBUGF | DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF) 485#define DAIF_STANDARD_DISABLE (DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF) 486 487#define SPSR_INTERRUPTS_ENABLED(x) (!(x & DAIF_FIQF)) 488 489#if HAS_ARM_FEAT_SSBS2 490#define PSR64_SSBS_U32_DEFAULT PSR64_SSBS_32 491#define PSR64_SSBS_U64_DEFAULT PSR64_SSBS_64 492#define PSR64_SSBS_KRN_DEFAULT PSR64_SSBS_64 493#else 494#define PSR64_SSBS_U32_DEFAULT (0) 495#define PSR64_SSBS_U64_DEFAULT (0) 496#define PSR64_SSBS_KRN_DEFAULT (0) 497#endif 498 499/* 500 * msr DAIFSet, Xn, and msr DAIFClr, Xn transfer 501 * from bits 3:0. 502 */ 503#define DAIFSC_DEBUGF (1 << 3) 504#define DAIFSC_ASYNCF (1 << 2) 505#define DAIFSC_IRQF (1 << 1) 506#define DAIFSC_FIQF (1 << 0) 507#define DAIFSC_ALL (DAIFSC_DEBUGF | DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF) 508#define DAIFSC_STANDARD_DISABLE (DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF) 509#define DAIFSC_NOASYNC (DAIFSC_DEBUGF | DAIFSC_IRQF | DAIFSC_FIQF) 510 511/* 512 * ARM64_TODO: unify with ARM? 513 */ 514#define PSR64_CF 0x20000000 /* Carry/Borrow/Extend */ 515 516#define PSR64_MODE_MASK 0x1F 517 518#define PSR64_USER_MASK PSR64_NZCV_MASK 519 520#define PSR64_MODE_USER32_THUMB 0x20 521 522#define PSR64_MODE_RW_SHIFT 4 523#define PSR64_MODE_RW_64 0 524#define PSR64_MODE_RW_32 (0x1 << PSR64_MODE_RW_SHIFT) 525 526#define PSR64_MODE_EL_SHIFT 2 527#define PSR64_MODE_EL_MASK (0x3 << PSR64_MODE_EL_SHIFT) 528#define PSR64_MODE_EL3 (0x3 << PSR64_MODE_EL_SHIFT) 529#define PSR64_MODE_EL2 (0x2 << PSR64_MODE_EL_SHIFT) 530#define PSR64_MODE_EL1 (0x1 << PSR64_MODE_EL_SHIFT) 531#define PSR64_MODE_EL0 0 532 533#define PSR64_MODE_EL_KERNEL (PSR64_MODE_EL1) 534 535#define PSR64_MODE_SPX 0x1 536#define PSR64_MODE_SP0 0 537 538#define PSR64_USER32_DEFAULT (PSR64_MODE_RW_32 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U32_DEFAULT) 539#define PSR64_USER64_DEFAULT (PSR64_MODE_RW_64 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U64_DEFAULT) 540#define PSR64_KERNEL_STANDARD (DAIF_STANDARD_DISABLE | PSR64_MODE_RW_64 | PSR64_MODE_EL1 | PSR64_MODE_SP0 | PSR64_SSBS_KRN_DEFAULT) 541#if __ARM_PAN_AVAILABLE__ 542#define PSR64_KERNEL_DEFAULT (PSR64_KERNEL_STANDARD | PSR64_PAN) 543#else 544#define PSR64_KERNEL_DEFAULT PSR64_KERNEL_STANDARD 545#endif 546 547#define PSR64_IS_KERNEL(x) ((x & PSR64_MODE_EL_MASK) > PSR64_MODE_EL0) 548#define PSR64_IS_USER(x) ((x & PSR64_MODE_EL_MASK) == PSR64_MODE_EL0) 549 550#define PSR64_IS_USER32(x) (PSR64_IS_USER(x) && (x & PSR64_MODE_RW_32)) 551#define PSR64_IS_USER64(x) (PSR64_IS_USER(x) && !(x & PSR64_MODE_RW_32)) 552 553 554 555/* 556 * System Control Register (SCTLR) 557 */ 558 559 560#if HAS_ARM_FEAT_SME 561// 60 EnTP2 Enable TPIDR2_EL0 at EL0 562#define SCTLR_TP2_ENABLED (1ULL << 60) 563#endif 564 565#define SCTLR_EPAN_ENABLED (1ULL << 57) 566 567#define SCTLR_DSSBS (1ULL << 44) 568 569 570#define SCTLR_EXTRA (0) 571 572 573#define SCTLR_RESERVED ((3ULL << 28) | (1ULL << 20)) 574#if defined(HAS_APPLE_PAC) 575 576// 31 PACIA_ENABLED AddPACIA and AuthIA functions enabled 577#define SCTLR_PACIA_ENABLED_SHIFT 31 578#define SCTLR_PACIA_ENABLED (1ULL << SCTLR_PACIA_ENABLED_SHIFT) 579// 30 PACIB_ENABLED AddPACIB and AuthIB functions enabled 580#define SCTLR_PACIB_ENABLED (1ULL << 30) 581// 29:28 RES1 11 582// 27 PACDA_ENABLED AddPACDA and AuthDA functions enabled 583#define SCTLR_PACDA_ENABLED (1ULL << 27) 584// 13 PACDB_ENABLED AddPACDB and AuthDB functions enabled 585#define SCTLR_PACDB_ENABLED (1ULL << 13) 586 587#define SCTLR_PAC_KEYS_ENABLED (SCTLR_PACIA_ENABLED | SCTLR_PACIB_ENABLED | SCTLR_PACDA_ENABLED | SCTLR_PACDB_ENABLED) 588#endif /* defined(HAS_APPLE_PAC) */ 589 590// 36 BT1 PACIxSP acts as a BTI C landing pad rather than BTI JC at EL1 591#define SCTLR_BT1_ENABLED (1ULL << 36) 592 593// 35 BT0 PACIxSP acts as a BTI C landing pad rather than BTI JC at EL0 594#define SCTLR_BT0_ENABLED (1ULL << 35) 595 596 597// 26 UCI User Cache Instructions 598#define SCTLR_UCI_ENABLED (1ULL << 26) 599 600// 25 EE Exception Endianness 601#define SCTLR_EE_BIG_ENDIAN (1ULL << 25) 602 603// 24 E0E EL0 Endianness 604#define SCTLR_E0E_BIG_ENDIAN (1ULL << 24) 605 606// 23 SPAN Set PAN 607#define SCTLR_PAN_UNCHANGED (1ULL << 23) 608 609// 22 EIS Taking an exception is a context synchronization event 610#define SCTLR_EIS (1ULL << 22) 611 612// 21 RES0 0 613// 20 RES1 1 614 615// 19 WXN Writeable implies eXecute Never 616#define SCTLR_WXN_ENABLED (1ULL << 19) 617 618// 18 nTWE Not trap WFE from EL0 619#define SCTLR_nTWE_WFE_ENABLED (1ULL << 18) 620 621// 17 RES0 0 622 623// 16 nTWI Not trap WFI from EL0 624#define SCTRL_nTWI_WFI_ENABLED (1ULL << 16) 625 626// 15 UCT User Cache Type register (CTR_EL0) 627#define SCTLR_UCT_ENABLED (1ULL << 15) 628 629// 14 DZE User Data Cache Zero (DC ZVA) 630#define SCTLR_DZE_ENABLED (1ULL << 14) 631 632// 12 I Instruction cache enable 633#define SCTLR_I_ENABLED (1ULL << 12) 634 635// 11 EOS Exception return is a context synchronization event 636#define SCTLR_EOS (1ULL << 11) 637 638// 10 EnRCTX EL0 Access to FEAT_SPECRES speculation restriction instructions 639#define SCTLR_EnRCTX (1ULL << 10) 640 641// 9 UMA User Mask Access 642#define SCTLR_UMA_ENABLED (1ULL << 9) 643 644// 8 SED SETEND Disable 645#define SCTLR_SED_DISABLED (1ULL << 8) 646 647// 7 ITD IT Disable 648#define SCTLR_ITD_DISABLED (1ULL << 7) 649 650// 6 RES0 0 651 652// 5 CP15BEN CP15 Barrier ENable 653#define SCTLR_CP15BEN_ENABLED (1ULL << 5) 654 655// 4 SA0 Stack Alignment check for EL0 656#define SCTLR_SA0_ENABLED (1ULL << 4) 657 658// 3 SA Stack Alignment check 659#define SCTLR_SA_ENABLED (1ULL << 3) 660 661// 2 C Cache enable 662#define SCTLR_C_ENABLED (1ULL << 2) 663 664// 1 A Alignment check 665#define SCTLR_A_ENABLED (1ULL << 1) 666 667// 0 M MMU enable 668#define SCTLR_M_ENABLED (1ULL << 0) 669 670#if APPLEVIRTUALPLATFORM 671#define SCTLR_EPAN_DEFAULT 0 672/* xnu tries to set SCTLR_EL1.EPAN = 1, but it may be RaZ/WI on some hosts */ 673#define SCTLR_EPAN_OPTIONAL SCTLR_EPAN_ENABLED 674#elif HAS_ARM_FEAT_PAN3 675#define SCTLR_EPAN_DEFAULT SCTLR_EPAN_ENABLED 676#define SCTLR_EPAN_OPTIONAL 0 677#else 678#define SCTLR_EPAN_DEFAULT 0 679#define SCTLR_EPAN_OPTIONAL 0 680#endif 681 682#if __ARM_ARCH_8_5__ 683#define SCTLR_EIS_DEFAULT (0) 684#define SCTLR_DSSBS_DEFAULT SCTLR_DSSBS 685#else 686#define SCTLR_EIS_DEFAULT (SCTLR_EIS) 687#define SCTLR_DSSBS_DEFAULT (0) 688#endif 689 690#if ERET_IS_NOT_CONTEXT_SYNCHRONIZING 691#define SCTLR_EOS_DEFAULT (0) 692#else 693#define SCTLR_EOS_DEFAULT (SCTLR_EOS) 694#endif 695 696#if HAS_APPLE_PAC 697#define SCTLR_PAC_KEYS_DEFAULT SCTLR_PAC_KEYS_ENABLED 698#else /* !HAS_APPLE_PAC */ 699#define SCTLR_PAC_KEYS_DEFAULT 0 700#endif 701 702#if BTI_ENFORCED 703/* In the kernel, we want PACIxSP to behave only as a BTI C */ 704#define SCTLR_BT_DEFAULT SCTLR_BT1_ENABLED 705#else 706#define SCTLR_BT_DEFAULT 0 707#endif /* BTI_ENFORCED */ 708 709#if HAS_ARM_FEAT_SME 710#define SCTLR_TP2_DEFAULT SCTLR_TP2_ENABLED 711#else 712#define SCTLR_TP2_DEFAULT 0 713#endif 714 715#define SCTLR_OTHER 0 716 717#define SCTLR_EL1_REQUIRED \ 718 (SCTLR_RESERVED | SCTLR_UCI_ENABLED | SCTLR_nTWE_WFE_ENABLED | SCTLR_DZE_ENABLED | \ 719 SCTLR_I_ENABLED | SCTLR_SED_DISABLED | SCTLR_CP15BEN_ENABLED | SCTLR_BT_DEFAULT | \ 720 SCTLR_SA0_ENABLED | SCTLR_SA_ENABLED | SCTLR_C_ENABLED | SCTLR_M_ENABLED | \ 721 SCTLR_EPAN_DEFAULT | SCTLR_EIS_DEFAULT | SCTLR_EOS_DEFAULT | SCTLR_DSSBS_DEFAULT | \ 722 SCTLR_PAC_KEYS_DEFAULT | SCTLR_TP2_DEFAULT | SCTLR_OTHER) 723 724#define SCTLR_EL1_OPTIONAL \ 725 (SCTLR_EPAN_OPTIONAL) 726 727#define SCTLR_EL1_DEFAULT \ 728 (SCTLR_EL1_REQUIRED | SCTLR_EL1_OPTIONAL) 729 730 731/* 732 * Coprocessor Access Control Register (CPACR) 733 * 734 * 31 28 27 22 21 20 19 0 735 * +---+---+------+------+--------------------+ 736 * |000|TTA|000000| FPEN |00000000000000000000| 737 * +---+---+------+------+--------------------+ 738 * 739 * where: 740 * TTA: Trace trap 741 * FPEN: Floating point enable 742 */ 743#define CPACR_TTA_SHIFT 28 744#define CPACR_TTA (1 << CPACR_TTA_SHIFT) 745 746#if HAS_ARM_FEAT_SME 747#define CPACR_SMEN_SHIFT 24 748#define CPACR_SMEN_MASK (0x3 << CPACR_SMEN_SHIFT) 749#define CPACR_SMEN_EL0_TRAP (0x1 << CPACR_SMEN_SHIFT) 750#define CPACR_SMEN_ENABLE (0x3 << CPACR_SMEN_SHIFT) 751#endif /* HAS_ARM_FEAT_SME */ 752 753#define CPACR_FPEN_SHIFT 20 754#define CPACR_FPEN_EL0_TRAP (0x1 << CPACR_FPEN_SHIFT) 755#define CPACR_FPEN_ENABLE (0x3 << CPACR_FPEN_SHIFT) 756 757#if HAS_ARM_FEAT_SME 758#define CPACR_ZEN_SHIFT 16 759#define CPACR_ZEN_MASK (0x3 << CPACR_ZEN_SHIFT) 760#define CPACR_ZEN_EL0_TRAP (0x1 << CPACR_ZEN_SHIFT) 761#define CPACR_ZEN_ENABLE (0x3 << CPACR_ZEN_SHIFT) 762#endif /* HAS_ARM_FEAT_SME */ 763 764/* 765 * FPSR: Floating Point Status Register 766 * 767 * 31 30 29 28 27 26 7 6 4 3 2 1 0 768 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+ 769 * | N| Z| C| V|QC|0000000000000000000|IDC|00|IXC|UFC|OFC|DZC|IOC| 770 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+ 771 */ 772 773#define FPSR_N_SHIFT 31 774#define FPSR_Z_SHIFT 30 775#define FPSR_C_SHIFT 29 776#define FPSR_V_SHIFT 28 777#define FPSR_QC_SHIFT 27 778#define FPSR_IDC_SHIFT 7 779#define FPSR_IXC_SHIFT 4 780#define FPSR_UFC_SHIFT 3 781#define FPSR_OFC_SHIFT 2 782#define FPSR_DZC_SHIFT 1 783#define FPSR_IOC_SHIFT 0 784#define FPSR_N (1 << FPSR_N_SHIFT) 785#define FPSR_Z (1 << FPSR_Z_SHIFT) 786#define FPSR_C (1 << FPSR_C_SHIFT) 787#define FPSR_V (1 << FPSR_V_SHIFT) 788#define FPSR_QC (1 << FPSR_QC_SHIFT) 789#define FPSR_IDC (1 << FPSR_IDC_SHIFT) 790#define FPSR_IXC (1 << FPSR_IXC_SHIFT) 791#define FPSR_UFC (1 << FPSR_UFC_SHIFT) 792#define FPSR_OFC (1 << FPSR_OFC_SHIFT) 793#define FPSR_DZC (1 << FPSR_DZC_SHIFT) 794#define FPSR_IOC (1 << FPSR_IOC_SHIFT) 795 796/* 797 * A mask for all for all of the bits that are not RAZ for FPSR; this 798 * is primarily for converting between a 32-bit view of NEON state 799 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR). 800 */ 801#define FPSR_MASK \ 802 (FPSR_N | FPSR_Z | FPSR_C | FPSR_V | FPSR_QC | FPSR_IDC | FPSR_IXC | \ 803 FPSR_UFC | FPSR_OFC | FPSR_DZC | FPSR_IOC) 804 805/* 806 * FPCR: Floating Point Control Register 807 * 808 * 31 26 25 24 23 21 19 18 15 14 12 11 10 9 8 7 0 809 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+ 810 * |00000|AHP|DN|FZ|RMODE|STRIDE| 0|LEN|IDE|00|IXE|UFE|OFE|DZE|IOE|00000000| 811 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+ 812 */ 813 814#define FPCR_AHP_SHIFT 26 815#define FPCR_DN_SHIFT 25 816#define FPCR_FZ_SHIFT 24 817#define FPCR_RMODE_SHIFT 22 818#define FPCR_STRIDE_SHIFT 20 819#define FPCR_LEN_SHIFT 16 820#define FPCR_IDE_SHIFT 15 821#define FPCR_IXE_SHIFT 12 822#define FPCR_UFE_SHIFT 11 823#define FPCR_OFE_SHIFT 10 824#define FPCR_DZE_SHIFT 9 825#define FPCR_IOE_SHIFT 8 826#define FPCR_AHP (1 << FPCR_AHP_SHIFT) 827#define FPCR_DN (1 << FPCR_DN_SHIFT) 828#define FPCR_FZ (1 << FPCR_FZ_SHIFT) 829#define FPCR_RMODE (0x3 << FPCR_RMODE_SHIFT) 830#define FPCR_STRIDE (0x3 << FPCR_STRIDE_SHIFT) 831#define FPCR_LEN (0x7 << FPCR_LEN_SHIFT) 832#define FPCR_IDE (1 << FPCR_IDE_SHIFT) 833#define FPCR_IXE (1 << FPCR_IXE_SHIFT) 834#define FPCR_UFE (1 << FPCR_UFE_SHIFT) 835#define FPCR_OFE (1 << FPCR_OFE_SHIFT) 836#define FPCR_DZE (1 << FPCR_DZE_SHIFT) 837#define FPCR_IOE (1 << FPCR_IOE_SHIFT) 838#define FPCR_DEFAULT (0) 839#define FPCR_DEFAULT_32 (FPCR_DN|FPCR_FZ) 840 841/* 842 * A mask for all for all of the bits that are not RAZ for FPCR; this 843 * is primarily for converting between a 32-bit view of NEON state 844 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR). 845 */ 846#define FPCR_MASK \ 847 (FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE | FPCR_STRIDE | FPCR_LEN | \ 848 FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE) 849 850/* 851 * Translation Control Register (TCR) 852 * 853 * Legacy: 854 * 855 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0 856 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+ 857 * | zero |TBI1|TBI0|AS|z| IPS |z|TG1| SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ |z|TG0| SH0 |ORGN0|IRGN0|EPD0|z|T0SZ| 858 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+ 859 * 860 * Current (with 16KB granule support): 861 * 862 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0 863 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+ 864 * | zero |TBI1|TBI0|AS|z| IPS | TG1 | SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ | TG0 | SH0 |ORGN0|IRGN0|EPD0|z|T0SZ| 865 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+ 866 * 867 * TBI1: Top Byte Ignored for TTBR1 region 868 * TBI0: Top Byte Ignored for TTBR0 region 869 * AS: ASID Size 870 * IPS: Physical Address Size limit 871 * TG1: Granule Size for TTBR1 region 872 * SH1: Shareability for TTBR1 region 873 * ORGN1: Outer Cacheability for TTBR1 region 874 * IRGN1: Inner Cacheability for TTBR1 region 875 * EPD1: Translation table walk disable for TTBR1 876 * A1: ASID selection from TTBR1 enable 877 * T1SZ: Virtual address size for TTBR1 878 * TG0: Granule Size for TTBR0 region 879 * SH0: Shareability for TTBR0 region 880 * ORGN0: Outer Cacheability for TTBR0 region 881 * IRGN0: Inner Cacheability for TTBR0 region 882 * T0SZ: Virtual address size for TTBR0 883 */ 884 885#define TCR_T0SZ_SHIFT 0ULL 886#define TCR_T0SZ_MASK 0x3FULL 887#define TCR_TSZ_BITS 6ULL 888#define TCR_TSZ_MASK ((1ULL << TCR_TSZ_BITS) - 1ULL) 889 890#define TCR_IRGN0_SHIFT 8ULL 891#define TCR_IRGN0_DISABLED (0ULL << TCR_IRGN0_SHIFT) 892#define TCR_IRGN0_WRITEBACK (1ULL << TCR_IRGN0_SHIFT) 893#define TCR_IRGN0_WRITETHRU (2ULL << TCR_IRGN0_SHIFT) 894#define TCR_IRGN0_WRITEBACKNO (3ULL << TCR_IRGN0_SHIFT) 895 896#define TCR_ORGN0_SHIFT 10ULL 897#define TCR_ORGN0_DISABLED (0ULL << TCR_ORGN0_SHIFT) 898#define TCR_ORGN0_WRITEBACK (1ULL << TCR_ORGN0_SHIFT) 899#define TCR_ORGN0_WRITETHRU (2ULL << TCR_ORGN0_SHIFT) 900#define TCR_ORGN0_WRITEBACKNO (3ULL << TCR_ORGN0_SHIFT) 901 902#define TCR_SH0_SHIFT 12ULL 903#define TCR_SH0_NONE (0ULL << TCR_SH0_SHIFT) 904#define TCR_SH0_OUTER (2ULL << TCR_SH0_SHIFT) 905#define TCR_SH0_INNER (3ULL << TCR_SH0_SHIFT) 906 907#define TCR_TG0_GRANULE_SHIFT (14ULL) 908#define TCR_TG0_GRANULE_BITS (2ULL) 909#define TCR_TG0_GRANULE_MASK ((1ULL << TCR_TG0_GRANULE_BITS) - 1ULL) 910 911#define TCR_TG0_GRANULE_4KB (0ULL << TCR_TG0_GRANULE_SHIFT) 912#define TCR_TG0_GRANULE_64KB (1ULL << TCR_TG0_GRANULE_SHIFT) 913#define TCR_TG0_GRANULE_16KB (2ULL << TCR_TG0_GRANULE_SHIFT) 914 915#if __ARM_16K_PG__ 916#define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_16KB) 917#else 918#define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_4KB) 919#endif 920 921#define TCR_T1SZ_SHIFT 16ULL 922#define TCR_T1SZ_MASK 0x3FULL 923 924#define TCR_A1_ASID1 (1ULL << 22ULL) 925#define TCR_EPD1_TTBR1_DISABLED (1ULL << 23ULL) 926 927#define TCR_IRGN1_SHIFT 24ULL 928#define TCR_IRGN1_DISABLED (0ULL << TCR_IRGN1_SHIFT) 929#define TCR_IRGN1_WRITEBACK (1ULL << TCR_IRGN1_SHIFT) 930#define TCR_IRGN1_WRITETHRU (2ULL << TCR_IRGN1_SHIFT) 931#define TCR_IRGN1_WRITEBACKNO (3ULL << TCR_IRGN1_SHIFT) 932 933#define TCR_ORGN1_SHIFT 26ULL 934#define TCR_ORGN1_DISABLED (0ULL << TCR_ORGN1_SHIFT) 935#define TCR_ORGN1_WRITEBACK (1ULL << TCR_ORGN1_SHIFT) 936#define TCR_ORGN1_WRITETHRU (2ULL << TCR_ORGN1_SHIFT) 937#define TCR_ORGN1_WRITEBACKNO (3ULL << TCR_ORGN1_SHIFT) 938 939#define TCR_SH1_SHIFT 28ULL 940#define TCR_SH1_NONE (0ULL << TCR_SH1_SHIFT) 941#define TCR_SH1_OUTER (2ULL << TCR_SH1_SHIFT) 942#define TCR_SH1_INNER (3ULL << TCR_SH1_SHIFT) 943 944#define TCR_TG1_GRANULE_SHIFT 30ULL 945#define TCR_TG1_GRANULE_BITS (2ULL) 946#define TCR_TG1_GRANULE_MASK ((1ULL << TCR_TG1_GRANULE_BITS) - 1ULL) 947 948#define TCR_TG1_GRANULE_16KB (1ULL << TCR_TG1_GRANULE_SHIFT) 949#define TCR_TG1_GRANULE_4KB (2ULL << TCR_TG1_GRANULE_SHIFT) 950#define TCR_TG1_GRANULE_64KB (3ULL << TCR_TG1_GRANULE_SHIFT) 951 952#if __ARM_16K_PG__ 953#define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_16KB) 954#else 955#define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_4KB) 956#endif 957 958#define TCR_IPS_SHIFT 32ULL 959#define TCR_IPS_BITS 3ULL 960#define TCR_IPS_MASK ((1ULL << TCR_IPS_BITS) - 1ULL) 961#define TCR_IPS_32BITS (0ULL << TCR_IPS_SHIFT) 962#define TCR_IPS_36BITS (1ULL << TCR_IPS_SHIFT) 963#define TCR_IPS_40BITS (2ULL << TCR_IPS_SHIFT) 964#define TCR_IPS_42BITS (3ULL << TCR_IPS_SHIFT) 965#define TCR_IPS_44BITS (4ULL << TCR_IPS_SHIFT) 966#define TCR_IPS_48BITS (5ULL << TCR_IPS_SHIFT) 967 968#define TCR_AS_16BIT_ASID (1ULL << 36) 969#define TCR_TBI0_TOPBYTE_IGNORED (1ULL << 37) 970#define TCR_TBI1_TOPBYTE_IGNORED (1ULL << 38) 971#define TCR_TBID0_TBI_DATA_ONLY (1ULL << 51) 972#define TCR_TBID1_TBI_DATA_ONLY (1ULL << 52) 973 974#if defined(HAS_APPLE_PAC) 975#define TCR_TBID0_ENABLE TCR_TBID0_TBI_DATA_ONLY 976#define TCR_TBID1_ENABLE TCR_TBID1_TBI_DATA_ONLY 977#else 978#define TCR_TBID0_ENABLE 0 979#define TCR_TBID1_ENABLE 0 980#endif 981 982#define TCR_E0PD0_BIT (1ULL << 55) 983#define TCR_E0PD1_BIT (1ULL << 56) 984 985#if defined(HAS_E0PD) 986#define TCR_E0PD_VALUE (TCR_E0PD1_BIT) 987#else 988#define TCR_E0PD_VALUE 0 989#endif 990 991 992#define TCR_EL1_EXTRA 0 993 994 995 996/* 997 * Multiprocessor Affinity Register (MPIDR_EL1) 998 * 999 * +64-----------------------------31+30+29-25+24+23-16+15-8+7--0+ 1000 * |000000000000000000000000000000001| U|00000|MT| Aff2|Aff1|Aff0| 1001 * +---------------------------------+--+-----+--+-----+----+----+ 1002 * 1003 * where 1004 * U: Uniprocessor 1005 * MT: Multi-threading at lowest affinity level 1006 * Aff2: "1" - PCORE, "0" - ECORE 1007 * Aff1: Cluster ID 1008 * Aff0: CPU ID 1009 */ 1010#define MPIDR_AFF0_SHIFT 0 1011#define MPIDR_AFF0_WIDTH 8 1012#define MPIDR_AFF0_MASK (((1 << MPIDR_AFF0_WIDTH) - 1) << MPIDR_AFF0_SHIFT) 1013#define MPIDR_AFF1_SHIFT 8 1014#define MPIDR_AFF1_WIDTH 8 1015#define MPIDR_AFF1_MASK (((1 << MPIDR_AFF1_WIDTH) - 1) << MPIDR_AFF1_SHIFT) 1016#define MPIDR_AFF2_SHIFT 16 1017#define MPIDR_AFF2_WIDTH 8 1018#define MPIDR_AFF2_MASK (((1 << MPIDR_AFF2_WIDTH) - 1) << MPIDR_AFF2_SHIFT) 1019 1020/* 1021 * TXSZ indicates the size of the range a TTBR covers. Currently, 1022 * we support the following: 1023 * 1024 * 4KB pages, full page L1: 39 bit range. 1025 * 4KB pages, sub-page L1: 38 bit range. 1026 * 16KB pages, full page L1: 47 bit range. 1027 * 16KB pages, sub-page L1: 39 bit range. 1028 * 16KB pages, two level page tables: 36 bit range. 1029 */ 1030#if __ARM_KERNEL_PROTECT__ 1031/* 1032 * If we are configured to use __ARM_KERNEL_PROTECT__, the first half of the 1033 * address space is used for the mappings that will remain in place when in EL0. 1034 * As a result, 1 bit less of address space is available to the rest of the 1035 * the kernel. 1036 */ 1037#endif /* __ARM_KERNEL_PROTECT__ */ 1038#ifdef __ARM_16K_PG__ 1039#if __ARM64_PMAP_SUBPAGE_L1__ 1040#define T0SZ_BOOT 25ULL 1041#else /* !__ARM64_PMAP_SUBPAGE_L1__ */ 1042#define T0SZ_BOOT 17ULL 1043#endif /* !__ARM64_PMAP_SUBPAGE_L1__ */ 1044#else /* __ARM_16K_PG__ */ 1045#if __ARM64_PMAP_SUBPAGE_L1__ 1046#define T0SZ_BOOT 26ULL 1047#else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1048#define T0SZ_BOOT 25ULL 1049#endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1050#endif /* __ARM_16K_PG__ */ 1051 1052#if __ARM64_PMAP_SUBPAGE_L1__ && CONFIG_SPTM 1053#define T0SZ_EARLY_BOOT 17ULL 1054#endif /*__ARM64_PMAP_SUBPAGE_L1__ && CONFIG_SPTM */ 1055 1056#if HAS_ARM_INDEPENDENT_TNSZ 1057#ifdef __ARM_16K_PG__ 1058#if __ARM64_PMAP_KERN_SUBPAGE_L1__ 1059#define T1SZ_BOOT 25ULL 1060#else /* !__ARM64_PMAP_KERN_SUBPAGE_L1__ */ 1061#define T1SZ_BOOT 17ULL 1062#endif /* !__ARM64_PMAP_KERN_SUBPAGE_L1__ */ 1063#else /* __ARM_16K_PG__ */ 1064#if __ARM64_PMAP_KERN_SUBPAGE_L1__ 1065#define T1SZ_BOOT 26ULL 1066#else /* __ARM64_PMAP_KERN_SUBPAGE_L1__ */ 1067#define T1SZ_BOOT 25ULL 1068#endif /*__ARM64_PMAP_KERN_SUBPAGE_L1__*/ 1069#endif /* __ARM_16K_PG__ */ 1070#else /* HAS_ARM_INDEPENDENT_TNSZ */ 1071#define T1SZ_BOOT T0SZ_BOOT 1072#endif /* HAS_ARM_INDEPENDENT_TNSZ */ 1073 1074#if __ARM_42BIT_PA_SPACE__ 1075#define TCR_IPS_VALUE TCR_IPS_42BITS 1076#else /* !__ARM_42BIT_PA_SPACE__ */ 1077#define TCR_IPS_VALUE TCR_IPS_40BITS 1078#endif /* !__ARM_42BIT_PA_SPACE__ */ 1079 1080#if CONFIG_KERNEL_TBI 1081#define TCR_EL1_DTBI (TCR_TBI1_TOPBYTE_IGNORED | TCR_TBID1_ENABLE) 1082#else /* CONFIG_KERNEL_TBI */ 1083#define TCR_EL1_DTBI 0 1084#endif /* CONFIG_KERNEL_TBI */ 1085 1086#if HAS_16BIT_ASID 1087#define TCR_EL1_ASID TCR_AS_16BIT_ASID 1088#else /* HAS_16BIT_ASID */ 1089#define TCR_EL1_ASID 0 1090#endif /* HAS_16BIT_ASID */ 1091 1092#define TCR_EL1_BASE \ 1093 (TCR_IPS_VALUE | TCR_SH0_OUTER | TCR_ORGN0_WRITEBACK | \ 1094 TCR_IRGN0_WRITEBACK | (T0SZ_BOOT << TCR_T0SZ_SHIFT) | \ 1095 TCR_SH1_OUTER | TCR_ORGN1_WRITEBACK | \ 1096 TCR_IRGN1_WRITEBACK | (TCR_TG1_GRANULE_SIZE) | \ 1097 TCR_TBI0_TOPBYTE_IGNORED | (TCR_TBID0_ENABLE) | TCR_E0PD_VALUE | \ 1098 TCR_EL1_DTBI | TCR_EL1_ASID | TCR_EL1_EXTRA) 1099 1100#if __ARM64_PMAP_SUBPAGE_L1__ && CONFIG_SPTM 1101#define TCR_EL1_BASE_BOOT \ 1102 (TCR_IPS_VALUE | TCR_SH0_OUTER | TCR_ORGN0_WRITEBACK | \ 1103 TCR_IRGN0_WRITEBACK | (T0SZ_EARLY_BOOT << TCR_T0SZ_SHIFT) | \ 1104 TCR_SH1_OUTER | TCR_ORGN1_WRITEBACK | \ 1105 TCR_IRGN1_WRITEBACK | (TCR_TG1_GRANULE_SIZE) | \ 1106 TCR_TBI0_TOPBYTE_IGNORED | (TCR_TBID0_ENABLE) | TCR_E0PD_VALUE | \ 1107 TCR_EL1_DTBI | TCR_EL1_ASID | TCR_EL1_EXTRA) 1108#endif /* __ARM64_PMAP_SUBPAGE_L1__ && CONFIG_SPTM */ 1109 1110#if __ARM_KERNEL_PROTECT__ 1111#define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1112#define T1SZ_USER (T1SZ_BOOT + 1) 1113#define TCR_EL1_USER (TCR_EL1_BASE | (T1SZ_USER << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1114#else 1115#if CONFIG_SPTM 1116#if __ARM64_PMAP_SUBPAGE_L1__ 1117#define TCR_EL1_BOOT (TCR_EL1_BASE_BOOT | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1118#define TCR_EL1_FINAL (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1119#else /* !__ARM64_PMAP_SUBPAGE_L1__ */ 1120#define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1121#define TCR_EL1_FINAL TCR_EL1_BOOT 1122#endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1123#else /* !CONFIG_SPTM */ 1124#define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1125#endif /* CONFIG_SPTM */ 1126#endif /* __ARM_KERNEL_PROTECT__ */ 1127 1128#define TCR_EL1_4KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_4KB)) 1129#define TCR_EL1_16KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_16KB)) 1130 1131/* 1132 * Bit 55 of the VA is used to select which TTBR to use during a translation table walk. 1133 */ 1134#define TTBR_SELECTOR (1ULL << 55) 1135 1136 1137 1138/* 1139 * Hypervisor Fine-Grained Read Trap Register (HFGRTR) 1140 */ 1141 1142#define HFGRTR_AMAIR2_SHIFT 63 1143#define HFGRTR_AMAIR2 (1ULL << HFGRTR_AMAIR2_SHIFT) 1144#define HFGRTR_MAIR2_SHIFT 62 1145#define HFGRTR_MAIR2 (1ULL << HFGRTR_MAIR2_SHIFT) 1146#define HFGRTR_S2POR_SHIFT 61 1147#define HFGRTR_S2POR (1ULL << HFGRTR_S2POR_SHIFT) 1148#define HFGRTR_POR_EL1_SHIFT 60 1149#define HFGRTR_POR_EL1 (1ULL << HFGRTR_POR_EL1_SHIFT) 1150#define HFGRTR_POR_EL0_SHIFT 59 1151#define HFGRTR_POR_EL0 (1ULL << HFGRTR_POR_EL0_SHIFT) 1152#define HFGRTR_PIR_SHIFT 58 1153#define HFGRTR_PIR (1ULL << HFGRTR_PIR_SHIFT) 1154#define HFGRTR_PIRE0_SHIFT 57 1155#define HFGRTR_PIRE0 (1ULL << HFGRTR_PIRE0_SHIFT) 1156#define HFGRTR_RCWMASK_SHIFT 56 1157#define HFGRTR_RCWMASK (1ULL << HFGRTR_RCWMASK_SHIFT) 1158#define HFGRTR_TPIDR2_SHIFT 55 1159#define HFGRTR_TPIDR2 (1ULL << HFGRTR_TPIDR2_SHIFT) 1160#define HFGRTR_SMPRI_SHIFT 54 1161#define HFGRTR_SMPRI (1ULL << HFGRTR_SMPRI_SHIFT) 1162#define HFGRTR_GCS_EL1_SHIFT 53 1163#define HFGRTR_GCS_EL1 (1ULL << HFGRTR_GCS_EL1_SHIFT) 1164#define HFGRTR_GCS_EL0_SHIFT 52 1165#define HFGRTR_GCS_EL0 (1ULL << HFGRTR_GCS_EL0_SHIFT) 1166#define HFGRTR_ACCDATA_SHIFT 50 1167#define HFGRTR_ACCDATA (1ULL << HFGRTR_ACCDATA_SHIFT) 1168#define HFGRTR_ERXADDR_SHIFT 49 1169#define HFGRTR_ERXADDR (1ULL << HFGRTR_ERXADDR_SHIFT) 1170#define HFGRTR_ERXPFGCDN_SHIFT 48 1171#define HFGRTR_ERXPFGCDN (1ULL << HFGRTR_ERXPFGCDN_SHIFT) 1172#define HFGRTR_ERXPFGCTL_SHIFT 47 1173#define HFGRTR_ERXPFGCTL (1ULL << HFGRTR_ERXPFGCTL_SHIFT) 1174#define HFGRTR_ERXPFGF_SHIFT 46 1175#define HFGRTR_ERXPFGF (1ULL << HFGRTR_ERXPFGF_SHIFT) 1176#define HFGRTR_ERXMISC_SHIFT 45 1177#define HFGRTR_ERXMISC (1ULL << HFGRTR_ERXMISC_SHIFT) 1178#define HFGRTR_ERXSTATUS_SHIFT 44 1179#define HFGRTR_ERXSTATUS (1ULL << HFGRTR_ERXSTATUS_SHIFT) 1180#define HFGRTR_ERXCTLR_SHIFT 43 1181#define HFGRTR_ERXCTLR (1ULL << HFGRTR_ERXCTLR_SHIFT) 1182#define HFGRTR_ERXFR_SHIFT 42 1183#define HFGRTR_ERXFR (1ULL << HFGRTR_ERXFR_SHIFT) 1184#define HFGRTR_ERRSELR_SHIFT 41 1185#define HFGRTR_ERRSELR (1ULL << HFGRTR_ERRSELR_SHIFT) 1186#define HFGRTR_ERRIDR_SHIFT 40 1187#define HFGRTR_ERRIDR (1ULL << HFGRTR_ERRIDR_SHIFT) 1188#define HFGRTR_ICC_IGRPEN_SHIFT 39 1189#define HFGRTR_ICC_IGRPEN (1ULL << HFGRTR_ICC_IGRPEN_SHIFT) 1190#define HFGRTR_VBAR_SHIFT 38 1191#define HFGRTR_VBAR (1ULL << HFGRTR_VBAR_SHIFT) 1192#define HFGRTR_TTBR1_SHIFT 37 1193#define HFGRTR_TTBR1 (1ULL << HFGRTR_TTBR1_SHIFT) 1194#define HFGRTR_TTBR0_SHIFT 36 1195#define HFGRTR_TTBR0 (1ULL << HFGRTR_TTBR0_SHIFT) 1196#define HFGRTR_TPIDR_EL0_SHIFT 35 1197#define HFGRTR_TPIDR_EL0 (1ULL << HFGRTR_TPIDR_EL0_SHIFT) 1198#define HFGRTR_TPIDRRO_SHIFT 34 1199#define HFGRTR_TPIDRRO (1ULL << HFGRTR_TPIDRRO_SHIFT) 1200#define HFGRTR_TPIDR_EL1_SHIFT 33 1201#define HFGRTR_TPIDR_EL1 (1ULL << HFGRTR_TPIDR_EL1_SHIFT) 1202#define HFGRTR_TCR_SHIFT 32 1203#define HFGRTR_TCR (1ULL << HFGRTR_TCR_SHIFT) 1204#define HFGRTR_SCXTNUM_EL0_SHIFT 31 1205#define HFGRTR_SCXTNUM_EL0 (1ULL << HFGRTR_SCXTNUM_EL0_SHIFT) 1206#define HFGRTR_SCXTNUM_EL1_SHIFT 30 1207#define HFGRTR_SCXTNUM_EL1 (1ULL << HFGRTR_SCXTNUM_EL1_SHIFT) 1208#define HFGRTR_SCTLR_SHIFT 29 1209#define HFGRTR_SCTLR (1ULL << HFGRTR_SCTLR_SHIFT) 1210#define HFGRTR_REVIDR_SHIFT 28 1211#define HFGRTR_REVIDR (1ULL << HFGRTR_REVIDR_SHIFT) 1212#define HFGRTR_PAR_SHIFT 27 1213#define HFGRTR_PAR (1ULL << HFGRTR_PAR_SHIFT) 1214#define HFGRTR_MPIDR_SHIFT 26 1215#define HFGRTR_MPIDR (1ULL << HFGRTR_MPIDR_SHIFT) 1216#define HFGRTR_MIDR_SHIFT 25 1217#define HFGRTR_MIDR (1ULL << HFGRTR_MIDR_SHIFT) 1218#define HFGRTR_MAIR_SHIFT 24 1219#define HFGRTR_MAIR (1ULL << HFGRTR_MAIR_SHIFT) 1220#define HFGRTR_LORSA_SHIFT 23 1221#define HFGRTR_LORSA (1ULL << HFGRTR_LORSA_SHIFT) 1222#define HFGRTR_LORN_SHIFT 22 1223#define HFGRTR_LORN (1ULL << HFGRTR_LORN_SHIFT) 1224#define HFGRTR_LORID_SHIFT 21 1225#define HFGRTR_LORID (1ULL << HFGRTR_LORID_SHIFT) 1226#define HFGRTR_LOREA_SHIFT 20 1227#define HFGRTR_LOREA (1ULL << HFGRTR_LOREA_SHIFT) 1228#define HFGRTR_LORC_SHIFT 19 1229#define HFGRTR_LORC (1ULL << HFGRTR_LORC_SHIFT) 1230#define HFGRTR_ISR_SHIFT 18 1231#define HFGRTR_ISR (1ULL << HFGRTR_ISR_SHIFT) 1232#define HFGRTR_FAR_SHIFT 17 1233#define HFGRTR_FAR (1ULL << HFGRTR_FAR_SHIFT) 1234#define HFGRTR_ESR_SHIFT 16 1235#define HFGRTR_ESR (1ULL << HFGRTR_ESR_SHIFT) 1236#define HFGRTR_DCZID_SHIFT 15 1237#define HFGRTR_DCZID (1ULL << HFGRTR_DCZID_SHIFT) 1238#define HFGRTR_CTR_SHIFT 14 1239#define HFGRTR_CTR (1ULL << HFGRTR_CTR_SHIFT) 1240#define HFGRTR_CSSELR_SHIFT 13 1241#define HFGRTR_CSSELR (1ULL << HFGRTR_CSSELR_SHIFT) 1242#define HFGRTR_CPACR_SHIFT 12 1243#define HFGRTR_CPACR (1ULL << HFGRTR_CPACR_SHIFT) 1244#define HFGRTR_CONTEXTIDR_SHIFT 11 1245#define HFGRTR_CONTEXTIDR (1ULL << HFGRTR_CONTEXTIDR_SHIFT) 1246#define HFGRTR_CLIDR_SHIFT 10 1247#define HFGRTR_CLIDR (1ULL << HFGRTR_CLIDR_SHIFT) 1248#define HFGRTR_CCSIDR_SHIFT 9 1249#define HFGRTR_CCSIDR (1ULL << HFGRTR_CCSIDR_SHIFT) 1250#define HFGRTR_APIBKEY_SHIFT 8 1251#define HFGRTR_APIBKEY (1ULL << HFGRTR_APIBKEY_SHIFT) 1252#define HFGRTR_APIAKEY_SHIFT 7 1253#define HFGRTR_APIAKEY (1ULL << HFGRTR_APIAKEY_SHIFT) 1254#define HFGRTR_APGAKEY_SHIFT 6 1255#define HFGRTR_APGAKEY (1ULL << HFGRTR_APGAKEY_SHIFT) 1256#define HFGRTR_APDBKEY_SHIFT 5 1257#define HFGRTR_APDBKEY (1ULL << HFGRTR_APDBKEY_SHIFT) 1258#define HFGRTR_APDAKEY_SHIFT 4 1259#define HFGRTR_APDAKEY (1ULL << HFGRTR_APDAKEY_SHIFT) 1260#define HFGRTR_AMAIR_SHIFT 3 1261#define HFGRTR_AMAIR (1ULL << HFGRTR_AMAIR_SHIFT) 1262#define HFGRTR_AIDR_SHIFT 2 1263#define HFGRTR_AIDR (1ULL << HFGRTR_AIDR_SHIFT) 1264#define HFGRTR_AFSR1_SHIFT 1 1265#define HFGRTR_AFSR1 (1ULL << HFGRTR_AFSR1_SHIFT) 1266#define HFGRTR_AFSR0_SHIFT 0 1267#define HFGRTR_AFSR0 (1ULL << HFGRTR_AFSR0_SHIFT) 1268 1269/* 1270 * Hypervisor Fine-Grained Write Trap Register (HFGWTR) 1271 */ 1272 1273#define HFGWTR_AMAIR2_SHIFT 63 1274#define HFGWTR_AMAIR2 (1ULL << HFGWTR_AMAIR2_SHIFT) 1275#define HFGWTR_MAIR2_SHIFT 62 1276#define HFGWTR_MAIR2 (1ULL << HFGWTR_MAIR2_SHIFT) 1277#define HFGWTR_S2POR_SHIFT 61 1278#define HFGWTR_S2POR (1ULL << HFGWTR_S2POR_SHIFT) 1279#define HFGWTR_POR_EL1_SHIFT 60 1280#define HFGWTR_POR_EL1 (1ULL << HFGWTR_POR_EL1_SHIFT) 1281#define HFGWTR_POR_EL0_SHIFT 59 1282#define HFGWTR_POR_EL0 (1ULL << HFGWTR_POR_EL0_SHIFT) 1283#define HFGWTR_PIR_SHIFT 58 1284#define HFGWTR_PIR (1ULL << HFGWTR_PIR_SHIFT) 1285#define HFGWTR_PIRE0_SHIFT 57 1286#define HFGWTR_PIRE0 (1ULL << HFGWTR_PIRE0_SHIFT) 1287#define HFGWTR_RCWMASK_SHIFT 56 1288#define HFGWTR_RCWMASK (1ULL << HFGWTR_RCWMASK_SHIFT) 1289#define HFGWTR_TPIDR2_SHIFT 55 1290#define HFGWTR_TPIDR2 (1ULL << HFGWTR_TPIDR2_SHIFT) 1291#define HFGWTR_SMPRI_SHIFT 54 1292#define HFGWTR_SMPRI (1ULL << HFGWTR_SMPRI_SHIFT) 1293#define HFGWTR_GCS_EL1_SHIFT 53 1294#define HFGWTR_GCS_EL1 (1ULL << HFGWTR_GCS_EL1_SHIFT) 1295#define HFGWTR_GCS_EL0_SHIFT 52 1296#define HFGWTR_GCS_EL0 (1ULL << HFGWTR_GCS_EL0_SHIFT) 1297#define HFGWTR_ACCDATA_SHIFT 50 1298#define HFGWTR_ACCDATA (1ULL << HFGWTR_ACCDATA_SHIFT) 1299#define HFGWTR_ERXADDR_SHIFT 49 1300#define HFGWTR_ERXADDR (1ULL << HFGWTR_ERXADDR_SHIFT) 1301#define HFGWTR_ERXPFGCDN_SHIFT 48 1302#define HFGWTR_ERXPFGCDN (1ULL << HFGWTR_ERXPFGCDN_SHIFT) 1303#define HFGWTR_ERXPFGCTL_SHIFT 47 1304#define HFGWTR_ERXPFGCTL (1ULL << HFGWTR_ERXPFGCTL_SHIFT) 1305#define HFGWTR_ERXMISC_SHIFT 45 1306#define HFGWTR_ERXMISC (1ULL << HFGWTR_ERXMISC_SHIFT) 1307#define HFGWTR_ERXSTATUS_SHIFT 44 1308#define HFGWTR_ERXSTATUS (1ULL << HFGWTR_ERXSTATUS_SHIFT) 1309#define HFGWTR_ERXCTLR_SHIFT 43 1310#define HFGWTR_ERXCTLR (1ULL << HFGWTR_ERXCTLR_SHIFT) 1311#define HFGWTR_ERRSELR_SHIFT 41 1312#define HFGWTR_ERRSELR (1ULL << HFGWTR_ERRSELR_SHIFT) 1313#define HFGWTR_ICC_IGRPEN_SHIFT 39 1314#define HFGWTR_ICC_IGRPEN (1ULL << HFGWTR_ICC_IGRPEN_SHIFT) 1315#define HFGWTR_VBAR_SHIFT 38 1316#define HFGWTR_VBAR (1ULL << HFGWTR_VBAR_SHIFT) 1317#define HFGWTR_TTBR1_SHIFT 37 1318#define HFGWTR_TTBR1 (1ULL << HFGWTR_TTBR1_SHIFT) 1319#define HFGWTR_TTBR0_SHIFT 36 1320#define HFGWTR_TTBR0 (1ULL << HFGWTR_TTBR0_SHIFT) 1321#define HFGWTR_TPIDR_EL0_SHIFT 35 1322#define HFGWTR_TPIDR_EL0 (1ULL << HFGWTR_TPIDR_EL0_SHIFT) 1323#define HFGWTR_TPIDRRO_SHIFT 34 1324#define HFGWTR_TPIDRRO (1ULL << HFGWTR_TPIDRRO_SHIFT) 1325#define HFGWTR_TPIDR_EL1_SHIFT 33 1326#define HFGWTR_TPIDR_EL1 (1ULL << HFGWTR_TPIDR_EL1_SHIFT) 1327#define HFGWTR_TCR_SHIFT 32 1328#define HFGWTR_TCR (1ULL << HFGWTR_TCR_SHIFT) 1329#define HFGWTR_SCXTNUM_EL0_SHIFT 31 1330#define HFGWTR_SCXTNUM_EL0 (1ULL << HFGWTR_SCXTNUM_EL0_SHIFT) 1331#define HFGWTR_SCXTNUM_EL1_SHIFT 30 1332#define HFGWTR_SCXTNUM_EL1 (1ULL << HFGWTR_SCXTNUM_EL1_SHIFT) 1333#define HFGWTR_SCXTNUM_SHIFT 30 1334#define HFGWTR_SCXTNUM (1ULL << HFGWTR_SCXTNUM_SHIFT) 1335#define HFGWTR_SCTLR_SHIFT 29 1336#define HFGWTR_SCTLR (1ULL << HFGWTR_SCTLR_SHIFT) 1337#define HFGWTR_PAR_SHIFT 27 1338#define HFGWTR_PAR (1ULL << HFGWTR_PAR_SHIFT) 1339#define HFGWTR_MAIR_SHIFT 24 1340#define HFGWTR_MAIR (1ULL << HFGWTR_MAIR_SHIFT) 1341#define HFGWTR_LORSA_SHIFT 23 1342#define HFGWTR_LORSA (1ULL << HFGWTR_LORSA_SHIFT) 1343#define HFGWTR_LORN_SHIFT 22 1344#define HFGWTR_LORN (1ULL << HFGWTR_LORN_SHIFT) 1345#define HFGWTR_LOREA_SHIFT 20 1346#define HFGWTR_LOREA (1ULL << HFGWTR_LOREA_SHIFT) 1347#define HFGWTR_LORC_SHIFT 19 1348#define HFGWTR_LORC (1ULL << HFGWTR_LORC_SHIFT) 1349#define HFGWTR_FAR_SHIFT 17 1350#define HFGWTR_FAR (1ULL << HFGWTR_FAR_SHIFT) 1351#define HFGWTR_ESR_SHIFT 16 1352#define HFGWTR_ESR (1ULL << HFGWTR_ESR_SHIFT) 1353#define HFGWTR_CSSELR_SHIFT 13 1354#define HFGWTR_CSSELR (1ULL << HFGWTR_CSSELR_SHIFT) 1355#define HFGWTR_CPACR_SHIFT 12 1356#define HFGWTR_CPACR (1ULL << HFGWTR_CPACR_SHIFT) 1357#define HFGWTR_CONTEXTIDR_SHIFT 11 1358#define HFGWTR_CONTEXTIDR (1ULL << HFGWTR_CONTEXTIDR_SHIFT) 1359#define HFGWTR_APIBKEY_SHIFT 8 1360#define HFGWTR_APIBKEY (1ULL << HFGWTR_APIBKEY_SHIFT) 1361#define HFGWTR_APIAKEY_SHIFT 7 1362#define HFGWTR_APIAKEY (1ULL << HFGWTR_APIAKEY_SHIFT) 1363#define HFGWTR_APGAKEY_SHIFT 6 1364#define HFGWTR_APGAKEY (1ULL << HFGWTR_APGAKEY_SHIFT) 1365#define HFGWTR_APDBKEY_SHIFT 5 1366#define HFGWTR_APDBKEY (1ULL << HFGWTR_APDBKEY_SHIFT) 1367#define HFGWTR_APDAKEY_SHIFT 4 1368#define HFGWTR_APDAKEY (1ULL << HFGWTR_APDAKEY_SHIFT) 1369#define HFGWTR_AMAIR_SHIFT 3 1370#define HFGWTR_AMAIR (1ULL << HFGWTR_AMAIR_SHIFT) 1371#define HFGWTR_AFSR1_SHIFT 1 1372#define HFGWTR_AFSR1 (1ULL << HFGWTR_AFSR1_SHIFT) 1373#define HFGWTR_AFSR0_SHIFT 0 1374#define HFGWTR_AFSR0 (1ULL << HFGWTR_AFSR0_SHIFT) 1375 1376/* 1377 * Monitor Debug System Control Register (MDSCR) 1378 */ 1379 1380#define MDSCR_TFO_SHIFT 31 1381#define MDSCR_TFO (1ULL << MDSCR_TFO_SHIFT) 1382#define MDSCR_RXFULL_SHIFT 30 1383#define MDSCR_RXFULL (1ULL << MDSCR_RXFULL_SHIFT) 1384#define MDSCR_TXFULL_SHIFT 29 1385#define MDSCR_TXFULL (1ULL << MDSCR_TXFULL_SHIFT) 1386#define MDSCR_RXO_SHIFT 27 1387#define MDSCR_RXO (1ULL << MDSCR_RXO_SHIFT) 1388#define MDSCR_TXU_SHIFT 26 1389#define MDSCR_TXU (1ULL << MDSCR_TXU_SHIFT) 1390#define MDSCR_INTDIS_SHIFT 22 1391#define MDSCR_INTDIS_MASK (0x2U << MDSCR_INTDIS_SHIFT) 1392#define MDSCR_TDA_SHIFT 21 1393#define MDSCR_TDA (1ULL << MDSCR_TDA_SHIFT) 1394#define MDSCR_SC2_SHIFT 19 1395#define MDSCR_SC2 (1ULL << MDSCR_SC2_SHIFT) 1396#define MDSCR_MDE_SHIFT 15 1397#define MDSCR_MDE (1ULL << MDSCR_MDE_SHIFT) 1398#define MDSCR_HDE_SHIFT 14 1399#define MDSCR_HDE (1ULL << MDSCR_HDE_SHIFT) 1400#define MDSCR_KDE_SHIFT 13 1401#define MDSCR_KDE (1ULL << MDSCR_KDE_SHIFT) 1402#define MDSCR_TDCC_SHIFT 12 1403#define MDSCR_TDCC (1ULL << MDSCR_TDCC_SHIFT) 1404#define MDSCR_ERR_SHIFT 6 1405#define MDSCR_ERR (1ULL << MDSCR_ERR_SHIFT) 1406#define MDSCR_SS_SHIFT 0 1407#define MDSCR_SS (1ULL << MDSCR_SS_SHIFT) 1408 1409/* 1410 * Hypervisor Debug Fine-Grained Read Trap Register (HDFGRTR_EL2) 1411 */ 1412#define HDFGRTR_PMBIDR_SHIFT 63 1413#define HDFGRTR_PMBIDR (1ULL << HDFGRTR_PMBIDR_SHIFT) 1414#define HDFGRTR_PMSNEVFR_SHIFT 62 1415#define HDFGRTR_PMSNEVFR (1ULL << HDFGRTR_PMSNEVFR_SHIFT) 1416#define HDFGRTR_BRBDATA_SHIFT 61 1417#define HDFGRTR_BRBDATA (1ULL << HDFGRTR_BRBDATA_SHIFT) 1418#define HDFGRTR_BRBCTL_SHIFT 60 1419#define HDFGRTR_BRBCTL (1ULL << HDFGRTR_BRBCTL_SHIFT) 1420#define HDFGRTR_BRBIDR_SHIFT 59 1421#define HDFGRTR_BRBIDR (1ULL << HDFGRTR_BRBIDR_SHIFT) 1422#define HDFGRTR_PMCEID_SHIFT 58 1423#define HDFGRTR_PMCEID (1ULL << HDFGRTR_PMCEID_SHIFT) 1424#define HDFGRTR_PMUSERENR_SHIFT 57 1425#define HDFGRTR_PMUSERENR (1ULL << HDFGRTR_PMUSERENR_SHIFT) 1426#define HDFGRTR_TRBTRG_SHIFT 56 1427#define HDFGRTR_TRBTRG (1ULL << HDFGRTR_TRBTRG_SHIFT) 1428#define HDFGRTR_TRBSR_SHIFT 55 1429#define HDFGRTR_TRBSR (1ULL << HDFGRTR_TRBSR_SHIFT) 1430#define HDFGRTR_TRBPTR_SHIFT 54 1431#define HDFGRTR_TRBPTR (1ULL << HDFGRTR_TRBPTR_SHIFT) 1432#define HDFGRTR_TRBMAR_SHIFT 53 1433#define HDFGRTR_TRBMAR (1ULL << HDFGRTR_TRBMAR_SHIFT) 1434#define HDFGRTR_TRBLIMITR_SHIFT 52 1435#define HDFGRTR_TRBLIMITR (1ULL << HDFGRTR_TRBLIMITR_SHIFT) 1436#define HDFGRTR_TRBIDR_SHIFT 51 1437#define HDFGRTR_TRBIDR (1ULL << HDFGRTR_TRBIDR_SHIFT) 1438#define HDFGRTR_TRBBASER_SHIFT 50 1439#define HDFGRTR_TRBBASER (1ULL << HDFGRTR_TRBBASER_SHIFT) 1440#define HDFGRTR_TRCVICTLR_SHIFT 48 1441#define HDFGRTR_TRCVICTLR (1ULL << HDFGRTR_TRCVICTLR_SHIFT) 1442#define HDFGRTR_TRCSTATR_SHIFT 47 1443#define HDFGRTR_TRCSTATR (1ULL << HDFGRTR_TRCSTATR_SHIFT) 1444#define HDFGRTR_TRCSSCSR_SHIFT 46 1445#define HDFGRTR_TRCSSCSR (1ULL << HDFGRTR_TRCSSCSR_SHIFT) 1446#define HDFGRTR_TRCSEQSTR_SHIFT 45 1447#define HDFGRTR_TRCSEQSTR (1ULL << HDFGRTR_TRCSEQSTR_SHIFT) 1448#define HDFGRTR_TRCPRGCTLR_SHIFT 44 1449#define HDFGRTR_TRCPRGCTLR (1ULL << HDFGRTR_TRCPRGCTLR_SHIFT) 1450#define HDFGRTR_TRCOSLSR_SHIFT 43 1451#define HDFGRTR_TRCOSLSR (1ULL << HDFGRTR_TRCOSLSR_SHIFT) 1452#define HDFGRTR_TRCIMSPEC_SHIFT 41 1453#define HDFGRTR_TRCIMSPEC (1ULL << HDFGRTR_TRCIMSPEC_SHIFT) 1454#define HDFGRTR_TRCID_SHIFT 40 1455#define HDFGRTR_TRCID (1ULL << HDFGRTR_TRCID_SHIFT) 1456#define HDFGRTR_TRCCNTVR_SHIFT 37 1457#define HDFGRTR_TRCCNTVR (1ULL << HDFGRTR_TRCCNTVR_SHIFT) 1458#define HDFGRTR_TRCCLAIM_SHIFT 36 1459#define HDFGRTR_TRCCLAIM (1ULL << HDFGRTR_TRCCLAIM_SHIFT) 1460#define HDFGRTR_TRCAUXCTLR_SHIFT 35 1461#define HDFGRTR_TRCAUXCTLR (1ULL << HDFGRTR_TRCAUXCTLR_SHIFT) 1462#define HDFGRTR_TRCAUTHSTATUS_SHIFT 34 1463#define HDFGRTR_TRCAUTHSTATUS (1ULL << HDFGRTR_TRCAUTHSTATUS_SHIFT) 1464#define HDFGRTR_TRC_SHIFT 33 1465#define HDFGRTR_TRC (1ULL << HDFGRTR_TRC_SHIFT) 1466#define HDFGRTR_PMSLATFR_SHIFT 32 1467#define HDFGRTR_PMSLATFR (1ULL << HDFGRTR_PMSLATFR_SHIFT) 1468#define HDFGRTR_PMSIRR_SHIFT 31 1469#define HDFGRTR_PMSIRR (1ULL << HDFGRTR_PMSIRR_SHIFT) 1470#define HDFGRTR_PMSIDR_SHIFT 30 1471#define HDFGRTR_PMSIDR (1ULL << HDFGRTR_PMSIDR_SHIFT) 1472#define HDFGRTR_PMSICR_SHIFT 29 1473#define HDFGRTR_PMSICR (1ULL << HDFGRTR_PMSICR_SHIFT) 1474#define HDFGRTR_PMSFCR_SHIFT 28 1475#define HDFGRTR_PMSFCR (1ULL << HDFGRTR_PMSFCR_SHIFT) 1476#define HDFGRTR_PMSEVFR_SHIFT 27 1477#define HDFGRTR_PMSEVFR (1ULL << HDFGRTR_PMSEVFR_SHIFT) 1478#define HDFGRTR_PMSCR_SHIFT 26 1479#define HDFGRTR_PMSCR (1ULL << HDFGRTR_PMSCR_SHIFT) 1480#define HDFGRTR_PMBSR_SHIFT 25 1481#define HDFGRTR_PMBSR (1ULL << HDFGRTR_PMBSR_SHIFT) 1482#define HDFGRTR_PMBPTR_SHIFT 24 1483#define HDFGRTR_PMBPTR (1ULL << HDFGRTR_PMBPTR_SHIFT) 1484#define HDFGRTR_PMBLIMITR_SHIFT 23 1485#define HDFGRTR_PMBLIMITR (1ULL << HDFGRTR_PMBLIMITR_SHIFT) 1486#define HDFGRTR_PMMIR_SHIFT 22 1487#define HDFGRTR_PMMIR (1ULL << HDFGRTR_PMMIR_SHIFT) 1488#define HDFGRTR_PMSELR_SHIFT 19 1489#define HDFGRTR_PMSELR (1ULL << HDFGRTR_PMSELR_SHIFT) 1490#define HDFGRTR_PMOVS_SHIFT 18 1491#define HDFGRTR_PMOVS (1ULL << HDFGRTR_PMOVS_SHIFT) 1492#define HDFGRTR_PMINTEN_SHIFT 17 1493#define HDFGRTR_PMINTEN (1ULL << HDFGRTR_PMINTEN_SHIFT) 1494#define HDFGRTR_PMCNTEN_SHIFT 16 1495#define HDFGRTR_PMCNTEN (1ULL << HDFGRTR_PMCNTEN_SHIFT) 1496#define HDFGRTR_PMCCNTR_SHIFT 15 1497#define HDFGRTR_PMCCNTR (1ULL << HDFGRTR_PMCCNTR_SHIFT) 1498#define HDFGRTR_PMCCFILTR_SHIFT 14 1499#define HDFGRTR_PMCCFILTR (1ULL << HDFGRTR_PMCCFILTR_SHIFT) 1500#define HDFGRTR_PMEVTYPER_SHIFT 13 1501#define HDFGRTR_PMEVTYPER (1ULL << HDFGRTR_PMEVTYPER_SHIFT) 1502#define HDFGRTR_PMEVCNTR_SHIFT 12 1503#define HDFGRTR_PMEVCNTR (1ULL << HDFGRTR_PMEVCNTR_SHIFT) 1504#define HDFGRTR_OSDLR_SHIFT 11 1505#define HDFGRTR_OSDLR (1ULL << HDFGRTR_OSDLR_SHIFT) 1506#define HDFGRTR_OSECCR_SHIFT 10 1507#define HDFGRTR_OSECCR (1ULL << HDFGRTR_OSECCR_SHIFT) 1508#define HDFGRTR_OSLSR_SHIFT 9 1509#define HDFGRTR_OSLSR (1ULL << HDFGRTR_OSLSR_SHIFT) 1510#define HDFGRTR_DBGPRCR_SHIFT 7 1511#define HDFGRTR_DBGPRCR (1ULL << HDFGRTR_DBGPRCR_SHIFT) 1512#define HDFGRTR_DBGAUTHSTATUS_SHIFT 6 1513#define HDFGRTR_DBGAUTHSTATUS (1ULL << HDFGRTR_DBGAUTHSTATUS_SHIFT) 1514#define HDFGRTR_DBGCLAIM_SHIFT 5 1515#define HDFGRTR_DBGCLAIM (1ULL << HDFGRTR_DBGCLAIM_SHIFT) 1516#define HDFGRTR_MDSCR_SHIFT 4 1517#define HDFGRTR_MDSCR (1ULL << HDFGRTR_MDSCR_SHIFT) 1518#define HDFGRTR_DBGWVR_SHIFT 3 1519#define HDFGRTR_DBGWVR (1ULL << HDFGRTR_DBGWVR_SHIFT) 1520#define HDFGRTR_DBGWCR_SHIFT 2 1521#define HDFGRTR_DBGWCR (1ULL << HDFGRTR_DBGWCR_SHIFT) 1522#define HDFGRTR_DBGBVR_SHIFT 1 1523#define HDFGRTR_DBGBVR (1ULL << HDFGRTR_DBGBVR_SHIFT) 1524#define HDFGRTR_DBGBCR_SHIFT 0 1525#define HDFGRTR_DBGBCR (1ULL << HDFGRTR_DBGBCR_SHIFT) 1526 1527/* 1528 * Hypervisor Debug Fine-Grained Write Trap Register (HDFGWTR_EL2) 1529 */ 1530#define HDFGWTR_PMSNEVFR_SHIFT 62 1531#define HDFGWTR_PMSNEVFR (1ULL << HDFGWTR_PMSNEVFR_SHIFT) 1532#define HDFGWTR_BRBDATA_SHIFT 61 1533#define HDFGWTR_BRBDATA (1ULL << HDFGWTR_BRBDATA_SHIFT) 1534#define HDFGWTR_BRBCTL_SHIFT 60 1535#define HDFGWTR_BRBCTL (1ULL << HDFGWTR_BRBCTL_SHIFT) 1536#define HDFGWTR_PMUSERENR_SHIFT 57 1537#define HDFGWTR_PMUSERENR (1ULL << HDFGWTR_PMUSERENR_SHIFT) 1538#define HDFGWTR_TRBTRG_SHIFT 56 1539#define HDFGWTR_TRBTRG (1ULL << HDFGWTR_TRBTRG_SHIFT) 1540#define HDFGWTR_TRBSR_SHIFT 55 1541#define HDFGWTR_TRBSR (1ULL << HDFGWTR_TRBSR_SHIFT) 1542#define HDFGWTR_TRBPTR_SHIFT 54 1543#define HDFGWTR_TRBPTR (1ULL << HDFGWTR_TRBPTR_SHIFT) 1544#define HDFGWTR_TRBMAR_SHIFT 53 1545#define HDFGWTR_TRBMAR (1ULL << HDFGWTR_TRBMAR_SHIFT) 1546#define HDFGWTR_TRBLIMITR_SHIFT 52 1547#define HDFGWTR_TRBLIMITR (1ULL << HDFGWTR_TRBLIMITR_SHIFT) 1548#define HDFGWTR_TRBBASER_SHIFT 50 1549#define HDFGWTR_TRBBASER (1ULL << HDFGWTR_TRBBASER_SHIFT) 1550#define HDFGWTR_TRFCR_SHIFT 49 1551#define HDFGWTR_TRFCR (1ULL << HDFGWTR_TRFCR_SHIFT) 1552#define HDFGWTR_TRCVICTLR_SHIFT 48 1553#define HDFGWTR_TRCVICTLR (1ULL << HDFGWTR_TRCVICTLR_SHIFT) 1554#define HDFGWTR_TRCSSCSR_SHIFT 46 1555#define HDFGWTR_TRCSSCSR (1ULL << HDFGWTR_TRCSSCSR_SHIFT) 1556#define HDFGWTR_TRCSEQSTR_SHIFT 45 1557#define HDFGWTR_TRCSEQSTR (1ULL << HDFGWTR_TRCSEQSTR_SHIFT) 1558#define HDFGWTR_TRCPRGCTLR_SHIFT 44 1559#define HDFGWTR_TRCPRGCTLR (1ULL << HDFGWTR_TRCPRGCTLR_SHIFT) 1560#define HDFGWTR_TRCOSLAR_SHIFT 42 1561#define HDFGWTR_TRCOSLAR (1ULL << HDFGWTR_TRCOSLAR_SHIFT) 1562#define HDFGWTR_TRCIMSPEC_SHIFT 41 1563#define HDFGWTR_TRCIMSPEC (1ULL << HDFGWTR_TRCIMSPEC_SHIFT) 1564#define HDFGWTR_TRCCNTVR_SHIFT 37 1565#define HDFGWTR_TRCCNTVR (1ULL << HDFGWTR_TRCCNTVR_SHIFT) 1566#define HDFGWTR_TRCCLAIM_SHIFT 36 1567#define HDFGWTR_TRCCLAIM (1ULL << HDFGWTR_TRCCLAIM_SHIFT) 1568#define HDFGWTR_TRCAUXCTLR_SHIFT 35 1569#define HDFGWTR_TRCAUXCTLR (1ULL << HDFGWTR_TRCAUXCTLR_SHIFT) 1570#define HDFGWTR_TRC_SHIFT 33 1571#define HDFGWTR_TRC (1ULL << HDFGWTR_TRC_SHIFT) 1572#define HDFGWTR_PMSLATFR_SHIFT 32 1573#define HDFGWTR_PMSLATFR (1ULL << HDFGWTR_PMSLATFR_SHIFT) 1574#define HDFGWTR_PMSIRR_SHIFT 31 1575#define HDFGWTR_PMSIRR (1ULL << HDFGWTR_PMSIRR_SHIFT) 1576#define HDFGWTR_PMSICR_SHIFT 29 1577#define HDFGWTR_PMSICR (1ULL << HDFGWTR_PMSICR_SHIFT) 1578#define HDFGWTR_PMSFCR_SHIFT 28 1579#define HDFGWTR_PMSFCR (1ULL << HDFGWTR_PMSFCR_SHIFT) 1580#define HDFGWTR_PMSEVFR_SHIFT 27 1581#define HDFGWTR_PMSEVFR (1ULL << HDFGWTR_PMSEVFR_SHIFT) 1582#define HDFGWTR_PMSCR_SHIFT 26 1583#define HDFGWTR_PMSCR (1ULL << HDFGWTR_PMSCR_SHIFT) 1584#define HDFGWTR_PMBSR_SHIFT 25 1585#define HDFGWTR_PMBSR (1ULL << HDFGWTR_PMBSR_SHIFT) 1586#define HDFGWTR_PMBPTR_SHIFT 24 1587#define HDFGWTR_PMBPTR (1ULL << HDFGWTR_PMBPTR_SHIFT) 1588#define HDFGWTR_PMBLIMITR_SHIFT 23 1589#define HDFGWTR_PMBLIMITR (1ULL << HDFGWTR_PMBLIMITR_SHIFT) 1590#define HDFGWTR_PMCR_SHIFT 21 1591#define HDFGWTR_PMCR (1ULL << HDFGWTR_PMCR_SHIFT) 1592#define HDFGWTR_PMSWINC_SHIFT 20 1593#define HDFGWTR_PMSWINC (1ULL << HDFGWTR_PMSWINC_SHIFT) 1594#define HDFGWTR_PMSELR_SHIFT 19 1595#define HDFGWTR_PMSELR (1ULL << HDFGWTR_PMSELR_SHIFT) 1596#define HDFGWTR_PMOVS_SHIFT 18 1597#define HDFGWTR_PMOVS (1ULL << HDFGWTR_PMOVS_SHIFT) 1598#define HDFGWTR_PMINTEN_SHIFT 17 1599#define HDFGWTR_PMINTEN (1ULL << HDFGWTR_PMINTEN_SHIFT) 1600#define HDFGWTR_PMCNTEN_SHIFT 16 1601#define HDFGWTR_PMCNTEN (1ULL << HDFGWTR_PMCNTEN_SHIFT) 1602#define HDFGWTR_PMCCNTR_SHIFT 15 1603#define HDFGWTR_PMCCNTR (1ULL << HDFGWTR_PMCCNTR_SHIFT) 1604#define HDFGWTR_PMCCFILTR_SHIFT 14 1605#define HDFGWTR_PMCCFILTR (1ULL << HDFGWTR_PMCCFILTR_SHIFT) 1606#define HDFGWTR_PMEVTYPER_SHIFT 13 1607#define HDFGWTR_PMEVTYPER (1ULL << HDFGWTR_PMEVTYPER_SHIFT) 1608#define HDFGWTR_PMEVCNTR_SHIFT 12 1609#define HDFGWTR_PMEVCNTR (1ULL << HDFGWTR_PMEVCNTR_SHIFT) 1610#define HDFGWTR_OSDLR_SHIFT 11 1611#define HDFGWTR_OSDLR (1ULL << HDFGWTR_OSDLR_SHIFT) 1612#define HDFGWTR_OSECCR_SHIFT 10 1613#define HDFGWTR_OSECCR (1ULL << HDFGWTR_OSECCR_SHIFT) 1614#define HDFGWTR_OSLAR_SHIFT 8 1615#define HDFGWTR_OSLAR (1ULL << HDFGWTR_OSLAR_SHIFT) 1616#define HDFGWTR_DBGPRCR_SHIFT 7 1617#define HDFGWTR_DBGPRCR (1ULL << HDFGWTR_DBGPRCR_SHIFT) 1618#define HDFGWTR_DBGCLAIM_SHIFT 5 1619#define HDFGWTR_DBGCLAIM (1ULL << HDFGWTR_DBGCLAIM_SHIFT) 1620#define HDFGWTR_MDSCR_SHIFT 4 1621#define HDFGWTR_MDSCR (1ULL << HDFGWTR_MDSCR_SHIFT) 1622#define HDFGWTR_DBGWVR_SHIFT 3 1623#define HDFGWTR_DBGWVR (1ULL << HDFGWTR_DBGWVR_SHIFT) 1624#define HDFGWTR_DBGWCR_SHIFT 2 1625#define HDFGWTR_DBGWCR (1ULL << HDFGWTR_DBGWCR_SHIFT) 1626#define HDFGWTR_DBGBVR_SHIFT 1 1627#define HDFGWTR_DBGBVR (1ULL << HDFGWTR_DBGBVR_SHIFT) 1628#define HDFGWTR_DBGBCR_SHIFT 0 1629#define HDFGWTR_DBGBCR (1ULL << HDFGWTR_DBGBCR_SHIFT) 1630 1631/* 1632 * Translation Table Base Register (TTBR) 1633 * 1634 * 63 48 47 x x-1 1 0 1635 * +--------+------------------+------+---+ 1636 * | ASID | Base Address | zero |CnP| 1637 * +--------+------------------+------+---+ 1638 * 1639 */ 1640#define TTBR_ASID_SHIFT 48 1641#define TTBR_ASID_MASK 0xffff000000000000 1642 1643#define TTBR_BADDR_MASK 0x0000fffffffffffe 1644#define TTBR_CNP 0x0000000000000001 1645 1646/* 1647 * Memory Attribute Indirection Register 1648 * 1649 * 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 1650 * +-------+-------+-------+-------+-------+-------+-------+-------+ 1651 * | Attr7 | Attr6 | Attr5 | Attr4 | Attr3 | Attr2 | Attr1 | Attr0 | 1652 * +-------+-------+-------+-------+-------+-------+-------+-------+ 1653 * 1654 */ 1655 1656#define MAIR_ATTR_SHIFT(x) (8*(x)) 1657 1658/* Strongly ordered or device memory attributes */ 1659#define MAIR_OUTER_STRONGLY_ORDERED 0x0 1660#define MAIR_OUTER_DEVICE 0x0 1661 1662#define MAIR_INNER_STRONGLY_ORDERED 0x0 1663#define MAIR_INNER_DEVICE 0x4 1664 1665/* Normal memory attributes */ 1666#define MAIR_OUTER_NON_CACHEABLE 0x40 1667#define MAIR_OUTER_WRITE_THROUGH 0x80 1668#define MAIR_OUTER_WRITE_BACK 0xc0 1669 1670#define MAIR_INNER_NON_CACHEABLE 0x4 1671#define MAIR_INNER_WRITE_THROUGH 0x8 1672#define MAIR_INNER_WRITE_BACK 0xc 1673 1674/* Allocate policy for cacheable memory */ 1675#define MAIR_OUTER_WRITE_ALLOCATE 0x10 1676#define MAIR_OUTER_READ_ALLOCATE 0x20 1677 1678#define MAIR_INNER_WRITE_ALLOCATE 0x1 1679#define MAIR_INNER_READ_ALLOCATE 0x2 1680 1681/* Memory Atribute Encoding */ 1682 1683/* 1684 * Device memory types: 1685 * G (gathering): multiple reads/writes can be combined 1686 * R (reordering): reads or writes may reach device out of program order 1687 * E (early-acknowledge): writes may return immediately (e.g. PCIe posted writes) 1688 */ 1689#if HAS_FEAT_XS 1690 1691#define MAIR_DISABLE_XS 0x00 /* Device Memory, nGnRnE (strongly ordered), XS=1 */ 1692#define MAIR_DISABLE 0x01 /* Device Memory, nGnRnE (strongly ordered), XS=0 */ 1693#define MAIR_POSTED_COMBINED_REORDERED_XS 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes), XS=1 */ 1694#define MAIR_POSTED_COMBINED_REORDERED 0x0D /* Device Memory, GRE (reorderable, gathered writes, posted writes), XS=0 */ 1695#define MAIR_WRITECOMB 0x40 /* Normal Memory, Non-Cacheable, XS=0 */ 1696#define MAIR_WRITETHRU 0xA0 /* Normal Memory, Write-through, XS=0 */ 1697#define MAIR_WRITEBACK 0xFF /* Normal Memory, Write-back, XS=0 */ 1698 1699 1700/* 1701 * Memory Attribute Index. If these values change, please also update the pmap 1702 * LLDB macros that rely on this value (e.g., PmapDecodeTTEARM64). 1703 */ 1704#define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled (normal memory) */ 1705#define CACHE_ATTRINDX_INNERWRITEBACK CACHE_ATTRINDX_WRITEBACK /* legacy compatibility only */ 1706#define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes (normal memory) */ 1707#define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled (normal memory) */ 1708#define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer (device memory), XS = 0 */ 1709#define CACHE_ATTRINDX_RESERVED 0x4 /* reserved for internal use */ 1710#define CACHE_ATTRINDX_DISABLE_XS 0x5 /* no cache, no buffer (device memory), XS = 1 */ 1711/** 1712 * Posted mappings use XS by default, and on newer Apple SoCs there is no fabric-level distinction 1713 * between early-ack and non-early-ack, so just alias POSTED to DISABLE_XS to save a MAIR index. 1714 */ 1715#define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE_XS 1716#define CACHE_ATTRINDX_POSTED_REORDERED CACHE_ATTRINDX_DISABLE /* no need for device-nGRE on newer SoCs, fallback to nGnRnE */ 1717#define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x6 /* no cache, write gathering, reorderable access, posted writes (device memory), XS=0 */ 1718#define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED_XS 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory), XS=1 */ 1719#define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 1720#define CACHE_ATTRINDX_N_INDICES (8ULL) 1721 1722#else 1723 1724#define MAIR_DISABLE 0x00 /* Device Memory, nGnRnE (strongly ordered) */ 1725#define MAIR_POSTED 0x04 /* Device Memory, nGnRE (strongly ordered, posted writes) */ 1726#define MAIR_POSTED_REORDERED 0x08 /* Device Memory, nGRE (reorderable, posted writes) */ 1727#define MAIR_POSTED_COMBINED_REORDERED 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes) */ 1728#define MAIR_WRITECOMB 0x44 /* Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable */ 1729#define MAIR_WRITETHRU 0xBB /* Normal Memory, Outer Write-through, Inner Write-through */ 1730#define MAIR_WRITEBACK 0xFF /* Normal Memory, Outer Write-back, Inner Write-back */ 1731 1732/* 1733 * Memory Attribute Index. If these values change, please also update the pmap 1734 * LLDB macros that rely on this value (e.g., PmapDecodeTTEARM64). 1735 */ 1736#define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled (normal memory) */ 1737#define CACHE_ATTRINDX_INNERWRITEBACK CACHE_ATTRINDX_WRITEBACK /* legacy compatibility only */ 1738#define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes (normal memory) */ 1739#define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled (normal memory) */ 1740#define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer (device memory) */ 1741#define CACHE_ATTRINDX_RESERVED 0x4 /* reserved for internal use */ 1742#define CACHE_ATTRINDX_POSTED 0x5 /* no cache, no buffer, posted writes (device memory) */ 1743#define CACHE_ATTRINDX_POSTED_REORDERED 0x6 /* no cache, reorderable access, posted writes (device memory) */ 1744#define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory) */ 1745#define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 1746#define CACHE_ATTRINDX_N_INDICES (8ULL) 1747 1748#endif /* HAS_FEAT_XS */ 1749 1750#if HAS_UCNORMAL_MEM || APPLEVIRTUALPLATFORM 1751#define CACHE_ATTRINDX_RT CACHE_ATTRINDX_WRITECOMB 1752#else 1753#define CACHE_ATTRINDX_RT CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 1754#endif /* HAS_UCNORMAL_MEM || APPLEVIRTUALPLATFORM */ 1755 1756 1757 1758/* 1759 * Access protection bit values (TTEs and PTEs), stage 1 1760 * 1761 * Bit 1 controls access type (1=RO, 0=RW), bit 0 controls user (1=access, 0=no access) 1762 */ 1763#define AP_RWNA 0x0 /* priv=read-write, user=no-access */ 1764#define AP_RWRW 0x1 /* priv=read-write, user=read-write */ 1765#define AP_RONA 0x2 /* priv=read-only, user=no-access */ 1766#define AP_RORO 0x3 /* priv=read-only, user=read-only */ 1767#define AP_MASK 0x3 /* mask to find ap bits */ 1768 1769/* 1770 * Shareability attributes 1771 */ 1772#define SH_NONE 0x0 /* Non shareable */ 1773#define SH_NONE 0x0 /* Device shareable */ 1774#define SH_DEVICE 0x2 /* Normal memory Inner non shareable - Outer non shareable */ 1775#define SH_OUTER_MEMORY 0x2 /* Normal memory Inner shareable - Outer shareable */ 1776#define SH_INNER_MEMORY 0x3 /* Normal memory Inner shareable - Outer non shareable */ 1777 1778 1779/* 1780 * ARM Page Granule 1781 */ 1782#ifdef __ARM_16K_PG__ 1783#define ARM_PGSHIFT 14 1784#else 1785#define ARM_PGSHIFT 12 1786#endif 1787#define ARM_PGBYTES (1 << ARM_PGSHIFT) 1788#define ARM_PGMASK (ARM_PGBYTES-1) 1789 1790/* 1791 * L0 Translation table 1792 * 1793 * 4KB granule size: 1794 * Each translation table is 4KB 1795 * 512 64-bit entries of 512GB (2^39) of address space. 1796 * Covers 256TB (2^48) of address space. 1797 * 1798 * 16KB granule size: 1799 * Each translation table is 16KB 1800 * 2 64-bit entries of 128TB (2^47) of address space. 1801 * Covers 256TB (2^48) of address space. 1802 */ 1803 1804/* 16K L0 */ 1805#define ARM_16K_TT_L0_SIZE 0x0000800000000000ULL /* size of area covered by a tte */ 1806#define ARM_16K_TT_L0_OFFMASK 0x00007fffffffffffULL /* offset within an L0 entry */ 1807#define ARM_16K_TT_L0_SHIFT 47 /* page descriptor shift */ 1808#define ARM_16K_TT_L0_INDEX_MASK 0x0000800000000000ULL /* mask for getting index in L0 table from virtual address */ 1809 1810/* 4K L0 */ 1811#define ARM_4K_TT_L0_SIZE 0x0000008000000000ULL /* size of area covered by a tte */ 1812#define ARM_4K_TT_L0_OFFMASK 0x0000007fffffffffULL /* offset within an L0 entry */ 1813#define ARM_4K_TT_L0_SHIFT 39 /* page descriptor shift */ 1814#define ARM_4K_TT_L0_INDEX_MASK 0x0000ff8000000000ULL /* mask for getting index in L0 table from virtual address */ 1815 1816/* 1817 * L1 Translation table 1818 * 1819 * 4KB granule size: 1820 * Each translation table is 4KB 1821 * 512 64-bit entries of 1GB (2^30) of address space. 1822 * Covers 512GB (2^39) of address space. 1823 * 1824 * 16KB granule size: 1825 * Each translation table is 16KB 1826 * 2048 64-bit entries of 64GB (2^36) of address space. 1827 * Covers 128TB (2^47) of address space. 1828 */ 1829 1830/* 16K L1 */ 1831#define ARM_16K_TT_L1_SIZE 0x0000001000000000ULL /* size of area covered by a tte */ 1832#define ARM_16K_TT_L1_OFFMASK 0x0000000fffffffffULL /* offset within an L1 entry */ 1833#define ARM_16K_TT_L1_SHIFT 36 /* page descriptor shift */ 1834#define ARM_16K_TT_L1_INDEX_MASK 0x00007ff000000000ULL 1835 1836/* 4K L1 */ 1837#define ARM_4K_TT_L1_SIZE 0x0000000040000000ULL /* size of area covered by a tte */ 1838#define ARM_4K_TT_L1_OFFMASK 0x000000003fffffffULL /* offset within an L1 entry */ 1839#define ARM_4K_TT_L1_SHIFT 30 /* page descriptor shift */ 1840 1841#define ARM_4K_TT_L1_INDEX_MASK 0x0000007fc0000000ULL 1842/* 1843 * Enable concatenated tables if: 1844 * 1. We have a 42-bit PA, and 1845 * 2. Either we're using 4k pages or mixed mode is supported. 1846 */ 1847#if __ARM_42BIT_PA_SPACE__ 1848#if !__ARM_16K_PG__ || __ARM_MIXED_PAGE_SIZE__ 1849/* IPA[39:30] mask for getting index into L1 concatenated table from virtual address */ 1850#define ARM_4K_TT_L1_40_BIT_CONCATENATED_INDEX_MASK 0x000000ffc0000000ULL 1851#endif /* !__ARM_16K_PG__ || __ARM_MIXED_PAGE_SIZE__ */ 1852#endif /* __ARM_42BIT_PA_SPACE__ */ 1853 1854/* some sugar for getting pointers to page tables and entries */ 1855#define L1_TABLE_T1_INDEX(va, tcr) (((va) & ARM_PTE_T1_REGION_MASK(tcr)) >> ARM_TT_L1_SHIFT) 1856#define L2_TABLE_INDEX(va) (((va) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT) 1857#define L3_TABLE_INDEX(va) (((va) & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT) 1858 1859#define L2_TABLE_VA(tte) ((tt_entry_t*) phystokv((*(tte)) & ARM_TTE_TABLE_MASK)) 1860#define L3_TABLE_VA(tte2) ((pt_entry_t*) phystokv((*(tte2)) & ARM_TTE_TABLE_MASK)) 1861 1862/* 1863 * L2 Translation table 1864 * 1865 * 4KB granule size: 1866 * Each translation table is 4KB 1867 * 512 64-bit entries of 2MB (2^21) of address space. 1868 * Covers 1GB (2^30) of address space. 1869 * 1870 * 16KB granule size: 1871 * Each translation table is 16KB 1872 * 2048 64-bit entries of 32MB (2^25) of address space. 1873 * Covers 64GB (2^36) of address space. 1874 */ 1875 1876/* 16K L2 */ 1877#define ARM_16K_TT_L2_SIZE 0x0000000002000000ULL /* size of area covered by a tte */ 1878#define ARM_16K_TT_L2_OFFMASK 0x0000000001ffffffULL /* offset within an L2 entry */ 1879#define ARM_16K_TT_L2_SHIFT 25 /* page descriptor shift */ 1880#define ARM_16K_TT_L2_INDEX_MASK 0x0000000ffe000000ULL /* mask for getting index in L2 table from virtual address */ 1881 1882/* 4K L2 */ 1883#define ARM_4K_TT_L2_SIZE 0x0000000000200000ULL /* size of area covered by a tte */ 1884#define ARM_4K_TT_L2_OFFMASK 0x00000000001fffffULL /* offset within an L2 entry */ 1885#define ARM_4K_TT_L2_SHIFT 21 /* page descriptor shift */ 1886#define ARM_4K_TT_L2_INDEX_MASK 0x000000003fe00000ULL /* mask for getting index in L2 table from virtual address */ 1887 1888/* 1889 * L3 Translation table 1890 * 1891 * 4KB granule size: 1892 * Each translation table is 4KB 1893 * 512 64-bit entries of 4KB (2^12) of address space. 1894 * Covers 2MB (2^21) of address space. 1895 * 1896 * 16KB granule size: 1897 * Each translation table is 16KB 1898 * 2048 64-bit entries of 16KB (2^14) of address space. 1899 * Covers 32MB (2^25) of address space. 1900 */ 1901 1902/* 16K L3 */ 1903#define ARM_16K_TT_L3_SIZE 0x0000000000004000ULL /* size of area covered by a tte */ 1904#define ARM_16K_TT_L3_OFFMASK 0x0000000000003fffULL /* offset within L3 PTE */ 1905#define ARM_16K_TT_L3_SHIFT 14 /* page descriptor shift */ 1906#define ARM_16K_TT_L3_INDEX_MASK 0x0000000001ffc000ULL /* mask for page descriptor index */ 1907 1908/* 4K L3 */ 1909#define ARM_4K_TT_L3_SIZE 0x0000000000001000ULL /* size of area covered by a tte */ 1910#define ARM_4K_TT_L3_OFFMASK 0x0000000000000fffULL /* offset within L3 PTE */ 1911#define ARM_4K_TT_L3_SHIFT 12 /* page descriptor shift */ 1912#define ARM_4K_TT_L3_INDEX_MASK 0x00000000001ff000ULL /* mask for page descriptor index */ 1913 1914#ifdef __ARM_16K_PG__ 1915 1916/* Native L0 defines */ 1917#define ARM_TT_L0_SIZE ARM_16K_TT_L0_SIZE 1918#define ARM_TT_L0_OFFMASK ARM_16K_TT_L0_OFFMASK 1919#define ARM_TT_L0_SHIFT ARM_16K_TT_L0_SHIFT 1920#define ARM_TT_L0_INDEX_MASK ARM_16K_TT_L0_INDEX_MASK 1921 1922/* Native L1 defines */ 1923#define ARM_TT_L1_SIZE ARM_16K_TT_L1_SIZE 1924#define ARM_TT_L1_OFFMASK ARM_16K_TT_L1_OFFMASK 1925#define ARM_TT_L1_SHIFT ARM_16K_TT_L1_SHIFT 1926#define ARM_TT_L1_INDEX_MASK ARM_16K_TT_L1_INDEX_MASK 1927 1928/* Native L2 defines */ 1929#define ARM_TT_L2_SIZE ARM_16K_TT_L2_SIZE 1930#define ARM_TT_L2_OFFMASK ARM_16K_TT_L2_OFFMASK 1931#define ARM_TT_L2_SHIFT ARM_16K_TT_L2_SHIFT 1932#define ARM_TT_L2_INDEX_MASK ARM_16K_TT_L2_INDEX_MASK 1933 1934/* Native L3 defines */ 1935#define ARM_TT_L3_SIZE ARM_16K_TT_L3_SIZE 1936#define ARM_TT_L3_OFFMASK ARM_16K_TT_L3_OFFMASK 1937#define ARM_TT_L3_SHIFT ARM_16K_TT_L3_SHIFT 1938#define ARM_TT_L3_INDEX_MASK ARM_16K_TT_L3_INDEX_MASK 1939 1940#else /* !__ARM_16K_PG__ */ 1941 1942/* Native L0 defines */ 1943#define ARM_TT_L0_SIZE ARM_4K_TT_L0_SIZE 1944#define ARM_TT_L0_OFFMASK ARM_4K_TT_L0_OFFMASK 1945#define ARM_TT_L0_SHIFT ARM_4K_TT_L0_SHIFT 1946#define ARM_TT_L0_INDEX_MASK ARM_4K_TT_L0_INDEX_MASK 1947 1948/* Native L1 defines */ 1949#define ARM_TT_L1_SIZE ARM_4K_TT_L1_SIZE 1950#define ARM_TT_L1_OFFMASK ARM_4K_TT_L1_OFFMASK 1951#define ARM_TT_L1_SHIFT ARM_4K_TT_L1_SHIFT 1952#define ARM_TT_L1_INDEX_MASK ARM_4K_TT_L1_INDEX_MASK 1953 1954/* Native L2 defines */ 1955#define ARM_TT_L2_SIZE ARM_4K_TT_L2_SIZE 1956#define ARM_TT_L2_OFFMASK ARM_4K_TT_L2_OFFMASK 1957#define ARM_TT_L2_SHIFT ARM_4K_TT_L2_SHIFT 1958#define ARM_TT_L2_INDEX_MASK ARM_4K_TT_L2_INDEX_MASK 1959 1960/* Native L3 defines */ 1961#define ARM_TT_L3_SIZE ARM_4K_TT_L3_SIZE 1962#define ARM_TT_L3_OFFMASK ARM_4K_TT_L3_OFFMASK 1963#define ARM_TT_L3_SHIFT ARM_4K_TT_L3_SHIFT 1964#define ARM_TT_L3_INDEX_MASK ARM_4K_TT_L3_INDEX_MASK 1965 1966#endif /* !__ARM_16K_PG__ */ 1967 1968/* 1969 * Convenience definitions for: 1970 * ARM_TT_LEAF: The last level of the configured page table format. 1971 * ARM_TT_TWIG: The second to last level of the configured page table format. 1972 * ARM_TT_ROOT: The first level of the configured page table format. 1973 * 1974 * My apologies to any botanists who may be reading this. 1975 */ 1976#define ARM_TT_LEAF_SIZE ARM_TT_L3_SIZE 1977#define ARM_TT_LEAF_OFFMASK ARM_TT_L3_OFFMASK 1978#define ARM_TT_LEAF_SHIFT ARM_TT_L3_SHIFT 1979#define ARM_TT_LEAF_INDEX_MASK ARM_TT_L3_INDEX_MASK 1980 1981#define ARM_TT_TWIG_SIZE ARM_TT_L2_SIZE 1982#define ARM_TT_TWIG_OFFMASK ARM_TT_L2_OFFMASK 1983#define ARM_TT_TWIG_SHIFT ARM_TT_L2_SHIFT 1984#define ARM_TT_TWIG_INDEX_MASK ARM_TT_L2_INDEX_MASK 1985 1986#define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE 1987#define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK 1988#define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT 1989#define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK 1990 1991/* 1992 * 4KB granule size: 1993 * 1994 * Level 0 Translation Table Entry 1995 * 1996 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1997 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1998 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V| 1999 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2000 * 2001 * Level 1 Translation Table Entry 2002 * 2003 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 2004 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2005 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V| 2006 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2007 * 2008 * Level 1 Translation Block Entry 2009 * 2010 * 63 59 58 55 54 53 52 51 48 47 30 29 12 11 10 9 8 7 6 5 4 2 1 0 2011 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 2012 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:30] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 2013 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 2014 * 2015 * Level 2 Translation Table Entry 2016 * 2017 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 2018 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2019 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V| 2020 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2021 * 2022 * Level 2 Translation Block Entry 2023 * 2024 * 63 59 58 55 54 53 52 51 48 47 21 20 12 11 10 9 8 7 6 5 4 2 1 0 2025 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 2026 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:21] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 2027 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 2028 * 2029 * 16KB granule size: 2030 * 2031 * Level 0 Translation Table Entry 2032 * 2033 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 2034 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2035 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V| 2036 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2037 * 2038 * Level 1 Translation Table Entry 2039 * 2040 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 2041 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2042 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V| 2043 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2044 * 2045 * Level 2 Translation Table Entry 2046 * 2047 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 2048 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2049 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V| 2050 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 2051 * 2052 * Level 2 Translation Block Entry 2053 * 2054 * 63 59 58 55 54 53 52 51 48 47 25 24 12 11 10 9 8 7 6 5 4 2 1 0 2055 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 2056 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:25] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 2057 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 2058 * 2059 * where: 2060 * nG: notGlobal bit 2061 * SH: Shareability field 2062 * AP: access protection 2063 * XN: eXecute Never bit 2064 * PXN: Privilege eXecute Never bit 2065 * NS: Non-Secure bit 2066 * HINT: 16 entry continuguous output hint 2067 * AttrIdx: Memory Attribute Index 2068 */ 2069 2070#define TTE_SHIFT 3 /* shift width of a tte (sizeof(tte) == (1 << TTE_SHIFT)) */ 2071#ifdef __ARM_16K_PG__ 2072#define TTE_PGENTRIES (16384 >> TTE_SHIFT) /* number of ttes per page */ 2073#else 2074#define TTE_PGENTRIES (4096 >> TTE_SHIFT) /* number of ttes per page */ 2075#endif 2076 2077#define ARM_TTE_MAX (TTE_PGENTRIES) 2078 2079#define ARM_TTE_EMPTY 0x0000000000000000ULL /* unasigned - invalid entry */ 2080#define ARM_TTE_TYPE_FAULT 0x0000000000000000ULL /* unasigned - invalid entry */ 2081 2082#define ARM_TTE_VALID 0x0000000000000001ULL /* valid entry */ 2083 2084#define ARM_TTE_TYPE_MASK 0x0000000000000002ULL /* mask for extracting the type */ 2085#define ARM_TTE_TYPE_TABLE 0x0000000000000002ULL /* page table type */ 2086#define ARM_TTE_TYPE_BLOCK 0x0000000000000000ULL /* block entry type */ 2087#define ARM_TTE_TYPE_L3BLOCK 0x0000000000000002ULL 2088 2089/* Base AttrIndx transforms */ 2090#define ARM_TTE_ATTRINDXSHIFT (2) 2091#define ARM_TTE_ATTRINDXBITS (0x7ULL) 2092#define ARM_TTE_ATTRINDX(x) (((x) & ARM_TTE_ATTRINDXBITS) << ARM_TTE_ATTRINDXSHIFT) /* memory attributes index */ 2093#define ARM_TTE_EXTRACT_ATTRINDX(x) (((x) >> ARM_TTE_ATTRINDXSHIFT) & ARM_TTE_ATTRINDXBITS) /* extract memory attributes index */ 2094#define ARM_TTE_ATTRINDXMASK ARM_TTE_ATTRINDX(ARM_TTE_ATTRINDXBITS) /* mask memory attributes index */ 2095#define ARM_TTE_ATTRINDX_AIE(x) 0ULL 2096#define ARM_TTE_ATTRINDXMASK_AIE 0ULL 2097#define ARM_TTE_EXTRACT_ATTRINDX_AIE(x) 0ULL 2098 2099#ifdef __ARM_16K_PG__ 2100/* 2101 * Note that L0/L1 block entries are disallowed for the 16KB granule size; what 2102 * are we doing with these? 2103 */ 2104#define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 16KB L3 TTE entry */ 2105#define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 128TB section */ 2106#define ARM_TTE_BLOCK_L1_MASK 0x0000fff000000000ULL /* mask to extract phys address from L1 block entry */ 2107#define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 64GB section */ 2108#define ARM_TTE_BLOCK_L2_MASK 0x0000fffffe000000ULL /* mask to extract phys address from Level 2 Translation Block entry */ 2109#define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 32MB section */ 2110#else 2111#define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 4KB L3 TTE entry */ 2112#define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 2048GB section */ 2113#define ARM_TTE_BLOCK_L1_MASK 0x0000ffffc0000000ULL /* mask to extract phys address from L1 block entry */ 2114#define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 1GB section */ 2115#define ARM_TTE_BLOCK_L2_MASK 0x0000ffffffe00000ULL /* mask to extract phys address from Level 2 Translation Block entry */ 2116#define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 2MB section */ 2117#endif 2118 2119#define ARM_TTE_BLOCK_APSHIFT 6 2120#define ARM_TTE_BLOCK_AP(x) ((x)<<ARM_TTE_BLOCK_APSHIFT) /* access protection */ 2121#define ARM_TTE_BLOCK_APMASK (0x3 << ARM_TTE_BLOCK_APSHIFT) 2122 2123#define ARM_TTE_BLOCK_ATTRINDX(x) (ARM_TTE_ATTRINDX_AIE(x) | ARM_TTE_ATTRINDX(x)) /* memory attributes index */ 2124#define ARM_TTE_BLOCK_ATTRINDXMASK (ARM_TTE_ATTRINDXMASK_AIE | ARM_TTE_ATTRINDXMASK) /* mask memory attributes index */ 2125 2126#define ARM_TTE_BLOCK_SH(x) ((x) << 8) /* access shared */ 2127#define ARM_TTE_BLOCK_SHMASK (0x3ULL << 8) /* mask access shared */ 2128 2129#define ARM_TTE_BLOCK_AF 0x0000000000000400ULL /* value for access */ 2130#define ARM_TTE_BLOCK_AFMASK 0x0000000000000400ULL /* access mask */ 2131 2132#define ARM_TTE_BLOCK_NG 0x0000000000000800ULL /* value for a global mapping */ 2133#define ARM_TTE_BLOCK_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */ 2134 2135#define ARM_TTE_BLOCK_NS 0x0000000000000020ULL /* value for a secure mapping */ 2136#define ARM_TTE_BLOCK_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */ 2137 2138#define ARM_TTE_BLOCK_PNX 0x0020000000000000ULL /* value for privilege no execute bit */ 2139#define ARM_TTE_BLOCK_PNXMASK 0x0020000000000000ULL /* privilege no execute mask */ 2140 2141#define ARM_TTE_BLOCK_NX 0x0040000000000000ULL /* value for no execute */ 2142#define ARM_TTE_BLOCK_NXMASK 0x0040000000000000ULL /* no execute mask */ 2143 2144#define ARM_TTE_BLOCK_WIRED 0x0400000000000000ULL /* value for software wired bit */ 2145#define ARM_TTE_BLOCK_WIREDMASK 0x0400000000000000ULL /* software wired mask */ 2146 2147#define ARM_TTE_BLOCK_WRITEABLE 0x0800000000000000ULL /* value for software writeable bit */ 2148#define ARM_TTE_BLOCK_WRITEABLEMASK 0x0800000000000000ULL /* software writeable mask */ 2149 2150#define ARM_TTE_TABLE_MASK 0x0000fffffffff000ULL /* mask for extracting pointer to next table (works at any level) */ 2151 2152#define ARM_TTE_TABLE_APSHIFT 61 2153#define ARM_TTE_TABLE_AP_MASK (0x3ULL << ARM_TTE_TABLE_APSHIFT) 2154#define ARM_TTE_TABLE_AP_NO_EFFECT 0x0ULL 2155#define ARM_TTE_TABLE_AP_USER_NA 0x1ULL 2156#define ARM_TTE_TABLE_AP_RO 0x2ULL 2157#define ARM_TTE_TABLE_AP_KERN_RO 0x3ULL 2158#define ARM_TTE_TABLE_AP(x) ((x) << ARM_TTE_TABLE_APSHIFT) /* access protection */ 2159 2160#define ARM_TTE_TABLE_NS 0x8000000000000020ULL /* value for a secure mapping */ 2161#define ARM_TTE_TABLE_NS_MASK 0x8000000000000020ULL /* notSecure mapping mask */ 2162 2163#define ARM_TTE_TABLE_XN 0x1000000000000000ULL /* value for no execute */ 2164#define ARM_TTE_TABLE_XNMASK 0x1000000000000000ULL /* no execute mask */ 2165 2166#define ARM_TTE_TABLE_PXN 0x0800000000000000ULL /* value for privilege no execute bit */ 2167#define ARM_TTE_TABLE_PXNMASK 0x0800000000000000ULL /* privilege execute mask */ 2168 2169/** Software use TTE bits which the kernel actually uses. */ 2170#define ARM_TTE_TABLE_SW_RESERVED_MASK (0x0000000000000000ULL) 2171 2172/** 2173 * Table TTE bits which must be set to zero by software when the TTE is valid. 2174 */ 2175#define ARM_TTE_TABLE_RESERVED_MASK \ 2176 (~(ARM_TTE_VALID | \ 2177 ARM_TTE_TYPE_MASK | \ 2178 ARM_TTE_TABLE_MASK | \ 2179 ARM_TTE_TABLE_SW_RESERVED_MASK | \ 2180 ARM_TTE_TABLE_PXNMASK | \ 2181 ARM_TTE_TABLE_XNMASK | \ 2182 ARM_TTE_TABLE_AP_MASK | \ 2183 ARM_TTE_TABLE_NS_MASK)) 2184 2185#if __ARM_KERNEL_PROTECT__ 2186#define ARM_TTE_BOOT_BLOCK_LOWER \ 2187 (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \ 2188 ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF | ARM_TTE_BLOCK_NG) 2189#else /* __ARM_KERNEL_PROTECT__ */ 2190#define ARM_TTE_BOOT_BLOCK_LOWER \ 2191 (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \ 2192 ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF) 2193#endif /* __ARM_KERNEL_PROTECT__ */ 2194#define ARM_TTE_BOOT_BLOCK_UPPER ARM_TTE_BLOCK_NX 2195 2196#define ARM_TTE_BOOT_TABLE (ARM_TTE_TYPE_TABLE | ARM_TTE_VALID ) 2197/* 2198 * L3 Translation table 2199 * 2200 * 4KB granule size: 2201 * Each translation table is 4KB 2202 * 512 64-bit entries of 4KB (2^12) of address space. 2203 * Covers 2MB (2^21) of address space. 2204 * 2205 * 16KB granule size: 2206 * Each translation table is 16KB 2207 * 2048 64-bit entries of 16KB (2^14) of address space. 2208 * Covers 32MB (2^25) of address space. 2209 */ 2210 2211#ifdef __ARM_16K_PG__ 2212#define ARM_PTE_SIZE 0x0000000000004000ULL /* size of area covered by a tte */ 2213#define ARM_PTE_OFFMASK 0x0000000000003fffULL /* offset within pte area */ 2214#define ARM_PTE_SHIFT 14 /* page descriptor shift */ 2215#define ARM_PTE_MASK 0x0000ffffffffc000ULL /* mask for output address in PTE */ 2216#else 2217#define ARM_PTE_SIZE 0x0000000000001000ULL /* size of area covered by a tte */ 2218#define ARM_PTE_OFFMASK 0x0000000000000fffULL /* offset within pte area */ 2219#define ARM_PTE_SHIFT 12 /* page descriptor shift */ 2220#define ARM_PTE_MASK 0x0000fffffffff000ULL /* mask for output address in PTE */ 2221#endif 2222 2223#define ARM_PTE_T0SZ(TCR) (((TCR) >> TCR_T0SZ_SHIFT) & TCR_T0SZ_MASK) 2224#define ARM_PTE_T1SZ(TCR) (((TCR) >> TCR_T1SZ_SHIFT) & TCR_T1SZ_MASK) 2225#define ARM_PTE_REGION_MASK(SZ) ((1ULL << (64 - (SZ))) - 1) 2226#define ARM_TTE_PA_MASK 0x0000fffffffff000ULL 2227 2228/* Handle Page table address bits in a TCR-aware way. */ 2229#define ARM_PTE_T0_REGION_MASK(TCR) (ARM_PTE_REGION_MASK(ARM_PTE_T0SZ(TCR))) 2230#define ARM_PTE_T1_REGION_MASK(TCR) (ARM_PTE_REGION_MASK(ARM_PTE_T1SZ(TCR))) 2231 2232/* 2233 * L3 Page table entries 2234 * 2235 * The following page table entry types are possible: 2236 * 2237 * fault page entry 2238 * 63 2 0 2239 * +------------------------------+--+ 2240 * | ignored |00| 2241 * +------------------------------+--+ 2242 * 2243 * 2244 * 63 59 58 55 54 53 52 51 50 47 48 12 11 10 9 8 7 6 5 4 2 1 0 2245 * +-----+------+--+---+----+---+--+----+----------------------+--+--+----+----+--+-------+-+-+ 2246 * | ign |sw use|XN|PXN|HINT|DBM|GP|zero| OutputAddress[47:12] |nG|AF| SH | AP |NS|AttrIdx|1|V| 2247 * +-----+------+--+---+----+---+--+----+----------------------+--+--+----+----+--+-------+-+-+ 2248 * 2249 * where: 2250 * nG: notGlobal bit 2251 * SH: Shareability field 2252 * AP: access protection 2253 * XN: eXecute Never bit 2254 * PXN: Privilege eXecute Never bit 2255 * NS: Non-Secure bit 2256 * HINT: 16 entry continuguous output hint 2257 * DBM: Dirty Bit Modifier 2258 * GP: Guraded Page 2259 * AttrIdx: Memory Attribute Index 2260 */ 2261 2262#define PTE_SHIFT 3 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */ 2263#ifdef __ARM_16K_PG__ 2264#define PTE_PGENTRIES (16384 >> PTE_SHIFT) /* number of ptes per page */ 2265#else 2266#define PTE_PGENTRIES (4096 >> PTE_SHIFT) /* number of ptes per page */ 2267#endif 2268 2269#define ARM_PTE_EMPTY 0x0000000000000000ULL /* unassigned - invalid entry */ 2270 2271/* markers for (invalid) PTE for a page sent to compressor */ 2272#define ARM_PTE_COMPRESSED 0x8000000000000000ULL /* compressed... */ 2273#define ARM_PTE_COMPRESSED_ALT 0x4000000000000000ULL /* ... and was "alt_acct" */ 2274#define ARM_PTE_COMPRESSED_MASK 0xC000000000000000ULL 2275 2276#define ARM_PTE_TYPE_VALID 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */ 2277#define ARM_PTE_TYPE_FAULT 0x0000000000000000ULL /* invalid L3 entry */ 2278#define ARM_PTE_TYPE_MASK 0x0000000000000003ULL /* mask to get pte type */ 2279 2280/* This mask works for both 16K and 4K pages because bits 12-13 will be zero in 16K pages */ 2281#define ARM_PTE_PAGE_MASK 0x0000FFFFFFFFF000ULL /* output address mask for page */ 2282#define ARM_PTE_PAGE_SHIFT 12 /* page shift for the output address in the entry */ 2283 2284#define ARM_PTE_AP(x) ((x) << 6) /* access protections */ 2285#define ARM_PTE_APMASK (0x3ULL << 6) /* mask access protections */ 2286#define ARM_PTE_EXTRACT_AP(x) (((x) >> 6) & 0x3ULL) /* extract access protections from PTE */ 2287 2288#define ARM_PTE_ATTRINDX(x) (uint64_t)(ARM_TTE_ATTRINDX_AIE(x) | ARM_TTE_ATTRINDX(x)) /* memory attributes index */ 2289#define ARM_PTE_ATTRINDXMASK (ARM_TTE_ATTRINDXMASK_AIE | ARM_TTE_ATTRINDXMASK) /* mask memory attributes index */ 2290#define ARM_PTE_EXTRACT_ATTRINDX(x) (ARM_TTE_EXTRACT_ATTRINDX_AIE(x) | ARM_TTE_EXTRACT_ATTRINDX(x)) /* extract memory attributes index */ 2291 2292#define ARM_PTE_SH(x) ((x) << 8) /* access shared */ 2293#define ARM_PTE_SHMASK (0x3ULL << 8) /* mask access shared */ 2294 2295#define ARM_PTE_AF 0x0000000000000400ULL /* value for access */ 2296#define ARM_PTE_AFMASK 0x0000000000000400ULL /* access mask */ 2297 2298#define ARM_PTE_NG 0x0000000000000800ULL /* value for a global mapping */ 2299#define ARM_PTE_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */ 2300 2301#define ARM_PTE_NS 0x0000000000000020ULL /* value for a secure mapping */ 2302#define ARM_PTE_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */ 2303 2304#define ARM_PTE_HINT 0x0010000000000000ULL /* value for contiguous entries hint */ 2305#define ARM_PTE_HINT_MASK 0x0010000000000000ULL /* mask for contiguous entries hint */ 2306 2307#define ARM_PTE_GP 0x0004000000000000ULL /* value marking a guarded page */ 2308#define ARM_PTE_GP_MASK 0x0004000000000000ULL /* mask for a guarded page mark */ 2309 2310#if __ARM_16K_PG__ 2311#define ARM_PTE_HINT_ENTRIES 128ULL /* number of entries the hint covers */ 2312#define ARM_PTE_HINT_ENTRIES_SHIFT 7ULL /* shift to construct the number of entries */ 2313#define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFE00000ULL /* mask to extract the starting hint address */ 2314#define ARM_PTE_HINT_ADDR_SHIFT 21 /* shift for the hint address */ 2315#define ARM_KVA_HINT_ADDR_MASK 0xFFFFFFFFFFE00000ULL /* mask to extract the starting hint address */ 2316#else 2317#define ARM_PTE_HINT_ENTRIES 16ULL /* number of entries the hint covers */ 2318#define ARM_PTE_HINT_ENTRIES_SHIFT 4ULL /* shift to construct the number of entries */ 2319#define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFFF0000ULL /* mask to extract the starting hint address */ 2320#define ARM_PTE_HINT_ADDR_SHIFT 16 /* shift for the hint address */ 2321#define ARM_KVA_HINT_ADDR_MASK 0xFFFFFFFFFFFF0000ULL /* mask to extract the starting hint address */ 2322#endif 2323 2324#define ARM_PTE_PNX 0x0020000000000000ULL /* value for privilege no execute bit */ 2325#define ARM_PTE_PXN ARM_PTE_PNX 2326#define ARM_PTE_PNXMASK 0x0020000000000000ULL /* privilege no execute mask */ 2327 2328#define ARM_PTE_NX 0x0040000000000000ULL /* value for no execute bit */ 2329#define ARM_PTE_XN ARM_PTE_NX 2330#define ARM_PTE_NXMASK 0x0040000000000000ULL /* no execute mask */ 2331 2332#define ARM_PTE_XMASK (ARM_PTE_PNXMASK | ARM_PTE_NXMASK) 2333 2334#define ARM_PTE_GUARDED 0x0004000000000000ULL /* value for "guarded"/BTI enforcing code page */ 2335#define ARM_PTE_GUARDED_MASK (PTE_GUARDED) 2336 2337#define ARM_PTE_WIRED 0x0400000000000000ULL /* value for software wired bit */ 2338#define ARM_PTE_WIRED_MASK 0x0400000000000000ULL /* software wired mask */ 2339 2340#define ARM_PTE_WRITEABLE 0x0800000000000000ULL /* value for software writeable bit */ 2341#define ARM_PTE_WRITEABLE_MASK 0x0800000000000000ULL /* software writeable mask */ 2342#define ARM_PTE_WRITABLE ARM_PTE_WRITEABLE 2343 2344/** Software use PTE bits which the kernel actually uses. */ 2345#define ARM_PTE_SW_RESERVED_MASK (ARM_PTE_WIRED_MASK | ARM_PTE_WRITEABLE_MASK) 2346 2347/** 2348 * PTE bits which must be set to zero by software when the PTE is valid. 2349 */ 2350#define ARM_PTE_RESERVED_MASK \ 2351 (~(ARM_PTE_TYPE_MASK | \ 2352 ARM_PTE_ATTRINDXMASK | \ 2353 ARM_PTE_NS_MASK | \ 2354 ARM_PTE_APMASK | \ 2355 ARM_PTE_SHMASK | \ 2356 ARM_PTE_AFMASK | \ 2357 ARM_PTE_NG_MASK | \ 2358 ARM_PTE_PAGE_MASK | \ 2359 ARM_PTE_GP_MASK | \ 2360 ARM_PTE_HINT_MASK | \ 2361 ARM_PTE_PNXMASK | \ 2362 ARM_PTE_NXMASK | \ 2363 ARM_PTE_SW_RESERVED_MASK)) 2364 2365#define ARM_PTE_BOOT_PAGE_BASE \ 2366 (ARM_PTE_TYPE_VALID | ARM_PTE_SH(SH_OUTER_MEMORY) | \ 2367 ARM_PTE_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_PTE_AF) 2368 2369#if __ARM_KERNEL_PROTECT__ 2370#define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE | ARM_PTE_NG) 2371#else /* __ARM_KERNEL_PROTECT__ */ 2372#define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE) 2373#endif /* __ARM_KERNEL_PROTECT__ */ 2374 2375/* 2376 * TLBI appers to only deal in 4KB page addresses, so give 2377 * it an explicit shift of 12. 2378 */ 2379#define TLBI_ADDR_SHIFT (0) 2380#define TLBI_ADDR_SIZE (44) 2381#define TLBI_ADDR_MASK ((1ULL << TLBI_ADDR_SIZE) - 1) 2382#define TLBI_IPA_SHIFT (0) 2383#define TLBI_IPA_SIZE (36) 2384#define TLBI_IPA_MASK ((1ULL << TLBI_IPA_SIZE) - 1) 2385#define TLBI_ASID_SHIFT (48) 2386#define TLBI_ASID_SIZE (16) 2387#define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1)) 2388 2389#define RTLBI_ADDR_SIZE (37) 2390#define RTLBI_ADDR_MASK ((1ULL << RTLBI_ADDR_SIZE) - 1) 2391#define RTLBI_ADDR_SHIFT ARM_TT_L3_SHIFT 2392#define RTLBI_TG(_page_shift_) ((uint64_t)((((_page_shift_) - 12) >> 1) + 1) << 46) 2393#define RTLBI_SCALE_SHIFT (44) 2394#define RTLBI_NUM_SHIFT (39) 2395 2396/* 2397 * RCTX instruction operand fields. 2398 */ 2399#define RCTX_EL_SHIFT (24) 2400#define RCTX_EL_SIZE (2) 2401#define RCTX_EL_MASK (((1ULL << RCTX_EL_SIZE) - 1) << RCTX_EL_SHIFT) 2402#define RCTX_EL(x) ((x << RCTX_EL_SHIFT) & RCTX_EL_MASK) 2403#define RCTX_ASID_SHIFT (0) 2404#define RCTX_ASID_SIZE (16) 2405#define RCTX_ASID_MASK (((1ULL << RCTX_ASID_SIZE) - 1) << RCTX_ASID_SHIFT) 2406#define RCTX_ASID(x) ((x << RCTX_ASID_SHIFT) & RCTX_ASID_MASK) 2407 2408/* 2409 * Exception Syndrome Register 2410 * 2411 * 63 56 55 32 31 26 25 24 0 2412 * +------+------+------+--+------------------+ 2413 * | RES0 | ISS2 | EC |IL| ISS | 2414 * +------+------+------+--+------------------+ 2415 * 2416 * RES0 - Reserved bits. 2417 * ISS2 - Instruction Specific Syndrome 2. 2418 * EC - Exception Class 2419 * IL - Instruction Length 2420 * ISS - Instruction Specific Syndrome 2421 * 2422 * Note: The ISS can have many forms. These are defined separately below. 2423 */ 2424 2425#define ESR_EC_SHIFT 26 2426#define ESR_EC_WIDTH 6 2427#define ESR_EC_MASK (0x3FULL << ESR_EC_SHIFT) 2428#define ESR_EC(x) ((x & ESR_EC_MASK) >> ESR_EC_SHIFT) 2429 2430#define ESR_IL_SHIFT 25 2431#define ESR_IL (1 << ESR_IL_SHIFT) 2432 2433#define ESR_INSTR_IS_2BYTES(x) (!(x & ESR_IL)) 2434 2435#define ESR_ISS_MASK 0x01FFFFFF 2436#define ESR_ISS(x) (x & ESR_ISS_MASK) 2437 2438 2439#ifdef __ASSEMBLER__ 2440/* Define only the classes we need to test in the exception vectors. */ 2441#define ESR_EC_UNCATEGORIZED 0x00 2442#define ESR_EC_BTI_FAIL 0x0D 2443#define ESR_EC_SVC_64 0x15 2444#define ESR_EC_HVC_64 0x16 2445#define ESR_EC_PAC_FAIL 0x1C 2446#define ESR_EC_IABORT_EL1 0x21 2447#define ESR_EC_DABORT_EL1 0x25 2448#define ESR_EC_SP_ALIGN 0x26 2449#define ESR_EC_BRK_AARCH64 0x3C 2450#else 2451typedef enum { 2452 ESR_EC_UNCATEGORIZED = 0x00, 2453 ESR_EC_WFI_WFE = 0x01, 2454 ESR_EC_MCR_MRC_CP15_TRAP = 0x03, 2455 ESR_EC_MCRR_MRRC_CP15_TRAP = 0x04, 2456 ESR_EC_MCR_MRC_CP14_TRAP = 0x05, 2457 ESR_EC_LDC_STC_CP14_TRAP = 0x06, 2458 ESR_EC_TRAP_SIMD_FP = 0x07, 2459 ESR_EC_PTRAUTH_INSTR_TRAP = 0x09, 2460 ESR_EC_MCRR_MRRC_CP14_TRAP = 0x0c, 2461 ESR_EC_BTI_FAIL = 0x0d, 2462 ESR_EC_ILLEGAL_INSTR_SET = 0x0e, 2463 ESR_EC_SVC_32 = 0x11, 2464 ESR_EC_HVC_32 = 0x12, 2465 ESR_EC_SVC_64 = 0x15, 2466 ESR_EC_HVC_64 = 0x16, 2467 ESR_EC_MSR_TRAP = 0x18, 2468#if __has_feature(ptrauth_calls) 2469 ESR_EC_PAC_FAIL = 0x1C, 2470#endif /* __has_feature(ptrauth_calls) */ 2471#if HAS_ARM_FEAT_SME 2472 ESR_EC_SME = 0x1D, 2473#endif 2474 ESR_EC_IABORT_EL0 = 0x20, 2475 ESR_EC_IABORT_EL1 = 0x21, 2476 ESR_EC_PC_ALIGN = 0x22, 2477 ESR_EC_DABORT_EL0 = 0x24, 2478 ESR_EC_DABORT_EL1 = 0x25, 2479 ESR_EC_SP_ALIGN = 0x26, 2480 ESR_EC_FLOATING_POINT_32 = 0x28, 2481 ESR_EC_FLOATING_POINT_64 = 0x2C, 2482 ESR_EC_SERROR_INTERRUPT = 0x2F, 2483 ESR_EC_BKPT_REG_MATCH_EL0 = 0x30, // Breakpoint Debug event taken to the EL from a lower EL. 2484 ESR_EC_BKPT_REG_MATCH_EL1 = 0x31, // Breakpoint Debug event taken to the EL from the EL. 2485 ESR_EC_SW_STEP_DEBUG_EL0 = 0x32, // Software Step Debug event taken to the EL from a lower EL. 2486 ESR_EC_SW_STEP_DEBUG_EL1 = 0x33, // Software Step Debug event taken to the EL from the EL. 2487 ESR_EC_WATCHPT_MATCH_EL0 = 0x34, // Watchpoint Debug event taken to the EL from a lower EL. 2488 ESR_EC_WATCHPT_MATCH_EL1 = 0x35, // Watchpoint Debug event taken to the EL from the EL. 2489 ESR_EC_BKPT_AARCH32 = 0x38, 2490 ESR_EC_BRK_AARCH64 = 0x3C, 2491} esr_exception_class_t; 2492 2493typedef enum { 2494 FSC_TRANSLATION_FAULT_L0 = 0x04, 2495 FSC_TRANSLATION_FAULT_L1 = 0x05, 2496 FSC_TRANSLATION_FAULT_L2 = 0x06, 2497 FSC_TRANSLATION_FAULT_L3 = 0x07, 2498 FSC_ACCESS_FLAG_FAULT_L1 = 0x09, 2499 FSC_ACCESS_FLAG_FAULT_L2 = 0x0A, 2500 FSC_ACCESS_FLAG_FAULT_L3 = 0x0B, 2501 FSC_PERMISSION_FAULT_L1 = 0x0D, 2502 FSC_PERMISSION_FAULT_L2 = 0x0E, 2503 FSC_PERMISSION_FAULT_L3 = 0x0F, 2504 FSC_SYNC_EXT_ABORT = 0x10, 2505 FSC_SYNC_EXT_ABORT_TT_L1 = 0x15, 2506 FSC_SYNC_EXT_ABORT_TT_L2 = 0x16, 2507 FSC_SYNC_EXT_ABORT_TT_L3 = 0x17, 2508 FSC_SYNC_PARITY = 0x18, 2509 FSC_ASYNC_PARITY = 0x19, 2510 FSC_SYNC_PARITY_TT_L1 = 0x1D, 2511 FSC_SYNC_PARITY_TT_L2 = 0x1E, 2512 FSC_SYNC_PARITY_TT_L3 = 0x1F, 2513 FSC_ALIGNMENT_FAULT = 0x21, 2514 FSC_DEBUG_FAULT = 0x22, 2515} fault_status_t; 2516#endif /* ASSEMBLER */ 2517 2518/* 2519 * SVC event 2520 * 24 16 15 0 2521 * +---------+-----+ 2522 * |000000000| IMM | 2523 * +---------+-----+ 2524 * 2525 * where: 2526 * IMM: Immediate value 2527 */ 2528 2529#define ISS_SVC_IMM_MASK 0xffff 2530#define ISS_SVC_IMM(x) ((x) & ISS_SVC_IMM_MASK) 2531 2532/* 2533 * HVC event 2534 * 24 16 15 0 2535 * +---------+-----+ 2536 * |000000000| IMM | 2537 * +---------+-----+ 2538 * 2539 * where: 2540 * IMM: Immediate value 2541 */ 2542 2543#define ISS_HVC_IMM_MASK 0xffff 2544#define ISS_HVC_IMM(x) ((x) & ISS_HVC_IMM_MASK) 2545 2546 2547/* 2548 * Software step debug event ISS (EL1) 2549 * 24 23 6 5 0 2550 * +---+-----------------+--+------+ 2551 * |ISV|00000000000000000|EX| IFSC | 2552 * +---+-----------------+--+------+ 2553 * 2554 * where: 2555 * ISV: Instruction syndrome valid 2556 * EX: Exclusive access 2557 * IFSC: Instruction Fault Status Code 2558 */ 2559 2560#define ISS_SSDE_ISV_SHIFT 24 2561#define ISS_SSDE_ISV (0x1 << ISS_SSDE_ISV_SHIFT) 2562 2563#define ISS_SSDE_EX_SHIFT 6 2564#define ISS_SSDE_EX (0x1 << ISS_SSDE_EX_SHIFT) 2565 2566#define ISS_SSDE_FSC_MASK 0x3F 2567#define ISS_SSDE_FSC(x) (x & ISS_SSDE_FSC_MASK) 2568 2569/* 2570 * Instruction Abort ISS (EL1) 2571 * 24 10 9 5 0 2572 * +--------------+---+--+---+------+ 2573 * |00000000000000|FnV|EA|000| IFSC | 2574 * +--------------+---+--+---+------+ 2575 * 2576 * where: 2577 * FnV: FAR not Valid 2578 * EA: External Abort type 2579 * IFSC: Instruction Fault Status Code 2580 */ 2581 2582#define ISS_IA_FNV_SHIFT 10 2583#define ISS_IA_FNV (0x1 << ISS_IA_FNV_SHIFT) 2584 2585#define ISS_IA_EA_SHIFT 9 2586#define ISS_IA_EA (0x1 << ISS_IA_EA_SHIFT) 2587 2588#define ISS_IA_FSC_MASK 0x3F 2589#define ISS_IA_FSC(x) (x & ISS_IA_FSC_MASK) 2590 2591 2592/* 2593 * Data Abort ISS (EL1) 2594 * 2595 * 24 10 9 8 7 6 5 0 2596 * +--------------+---+--+--+-----+---+----+ 2597 * |00000000000000|FnV|EA|CM|S1PTW|WnR|DFSC| 2598 * +--------------+---+--+--+-----+---+----+ 2599 * 2600 * where: 2601 * FnV: FAR not Valid 2602 * EA: External Abort type 2603 * CM: Cache Maintenance operation 2604 * WnR: Write not Read 2605 * S1PTW: Stage 2 exception on Stage 1 page table walk 2606 * DFSC: Data Fault Status Code 2607 */ 2608#define ISS_DA_FNV_SHIFT 10 2609#define ISS_DA_FNV (0x1 << ISS_DA_FNV_SHIFT) 2610 2611#define ISS_DA_ISV_SHIFT 24 2612#define ISS_DA_ISV (0x1 << ISS_DA_ISV_SHIFT) 2613 2614#define ISS_DA_SAS_MASK 0x3 2615#define ISS_DA_SAS_SHIFT 22 2616#define ISS_DA_SAS(x) (((x) >> ISS_DA_SAS_SHIFT) & ISS_DA_SAS_MASK) 2617 2618#define ISS_DA_SRT_MASK 0x1f 2619#define ISS_DA_SRT_SHIFT 16 2620#define ISS_DA_SRT(x) (((x) >> ISS_DA_SRT_SHIFT) & ISS_DA_SRT_MASK) 2621 2622#define ISS_DA_EA_SHIFT 9 2623#define ISS_DA_EA (0x1 << ISS_DA_EA_SHIFT) 2624 2625#define ISS_DA_CM_SHIFT 8 2626#define ISS_DA_CM (0x1 << ISS_DA_CM_SHIFT) 2627 2628#define ISS_DA_WNR_SHIFT 6 2629#define ISS_DA_WNR (0x1 << ISS_DA_WNR_SHIFT) 2630 2631#define ISS_DA_S1PTW_SHIFT 7 2632#define ISS_DA_S1PTW (0x1 << ISS_DA_S1PTW_SHIFT) 2633 2634#define ISS_DA_FSC_MASK 0x3F 2635#define ISS_DA_FSC(x) (x & ISS_DA_FSC_MASK) 2636 2637/* 2638 * Floating Point Exception ISS (EL1) 2639 * 2640 * 24 23 22 8 7 4 3 2 1 0 2641 * +-+---+---------------+---+--+---+---+---+---+---+ 2642 * |0|TFV|000000000000000|IDF|00|IXF|UFF|OFF|DZF|IOF| 2643 * +-+---+---------------+---+--+---+---+---+---+---+ 2644 * 2645 * where: 2646 * TFV: Trapped Fault Valid 2647 * IDF: Input Denormal Exception 2648 * IXF: Input Inexact Exception 2649 * UFF: Underflow Exception 2650 * OFF: Overflow Exception 2651 * DZF: Divide by Zero Exception 2652 * IOF: Invalid Operation Exception 2653 */ 2654#define ISS_FP_TFV_SHIFT 23 2655#define ISS_FP_TFV (0x1 << ISS_FP_TFV_SHIFT) 2656 2657#define ISS_FP_IDF_SHIFT 7 2658#define ISS_FP_IDF (0x1 << ISS_FP_IDF_SHIFT) 2659 2660#define ISS_FP_IXF_SHIFT 4 2661#define ISS_FP_IXF (0x1 << ISS_FP_IXF_SHIFT) 2662 2663#define ISS_FP_UFF_SHIFT 3 2664#define ISS_FP_UFF (0x1 << ISS_FP_UFF_SHIFT) 2665 2666#define ISS_FP_OFF_SHIFT 2 2667#define ISS_FP_OFF (0x1 << ISS_FP_OFF_SHIFT) 2668 2669#define ISS_FP_DZF_SHIFT 1 2670#define ISS_FP_DZF (0x1 << ISS_FP_DZF_SHIFT) 2671 2672#define ISS_FP_IOF_SHIFT 0 2673#define ISS_FP_IOF (0x1 << ISS_FP_IOF_SHIFT) 2674 2675/* 2676 * Breakpoint Exception ISS (EL1) 2677 * 24 16 0 2678 * +---------+---------+ 2679 * |000000000| Comment | 2680 * +---------+---------+ 2681 * 2682 * where: 2683 * Comment: Instruction Comment Field Value 2684 */ 2685#define ISS_BRK_COMMENT_MASK 0xFFFF 2686#define ISS_BRK_COMMENT(x) (x & ISS_BRK_COMMENT_MASK) 2687 2688 2689 2690/* 2691 * SError Interrupt, IDS=1 2692 * 24 23 0 2693 * +---+------------------------+ 2694 * |IDS| IMPLEMENTATION DEFINED | 2695 * +---+------------------------+ 2696 * 2697 * where: 2698 * IDS: Implementation-defined syndrome (1) 2699 */ 2700 2701#define ISS_SEI_IDS_SHIFT 24 2702#define ISS_SEI_IDS (0x1 << ISS_SEI_IDS_SHIFT) 2703 2704 2705#if HAS_UCNORMAL_MEM 2706#define ISS_UC 0x11 2707#endif /* HAS_UCNORMAL_MEM */ 2708 2709 2710 2711#if HAS_ARM_FEAT_SME 2712 2713/* 2714 * SME ISS (EL1) 2715 * 2716 * 24 3 2 0 2717 * +----------------------+----+ 2718 * |0000000000000000000000|SMTC| 2719 * +----------------------+----+ 2720 * 2721 * where: 2722 * SMTC: SME Trap Code 2723 */ 2724#define ISS_SME_SMTC_CAPCR 0x0 2725#define ISS_SME_SMTC_MASK 0x7 2726#define ISS_SME_SMTC(x) ((x) & ISS_SME_SMTC_MASK) 2727 2728 2729/* 2730 * SME Control Register (EL1) 2731 * 31 30 29 4 3 0 2732 * +----+----+--------------------------+---+ 2733 * |FA64|EZT0|00000000000000000000000000|LEN| 2734 * +----+----+--------------------------+---+ 2735 * 2736 * where: 2737 * FA64: Enable FEAT_SME_FA64 2738 * EZT0: Enable ZT0 2739 * LEN: Effective SVL = (LEN + 1) * 128 2740 */ 2741 2742#define SMCR_EL1_LEN_MASK 0xf 2743#if HAS_ARM_FEAT_SME2 2744#define SMCR_EL1_EZT0 (1ULL << 30) 2745#endif 2746#define SMCR_EL1_LEN(x) ((x) & SMCR_EL1_LEN_MASK) 2747 2748#define SMPRI_EL1_PRIORITY_MASK 0xf 2749#define SMPRI_EL1_PRIORITY(x) ((x) & SMPRI_EL1_PRIORITY_MASK) 2750 2751/* 2752 * Streaming Vector Control Register (SVCR) 2753 */ 2754#define SVCR_ZA_SHIFT (1) 2755#define SVCR_ZA (1ULL << SVCR_ZA_SHIFT) 2756#define SVCR_SM_SHIFT (0) 2757#define SVCR_SM (1ULL << SVCR_SM_SHIFT) 2758 2759#endif /* HAS_ARM_FEAT_SME */ 2760 2761/* 2762 * Branch Target Indication Exception ISS 2763 * 24 3 2 0 2764 * +----+-----+ 2765 * |res0|BTYPE| 2766 * +----+-----+ 2767 */ 2768#define ISS_BTI_BTYPE_SHIFT (0) 2769#define ISS_BTI_BTYPE_MASK (0x3 << ISS_BTI_BTYPE_SHIFT) 2770 2771/* 2772 * Physical Address Register (EL1) 2773 */ 2774#define PAR_F_SHIFT 0 2775#define PAR_F (0x1 << PAR_F_SHIFT) 2776 2777#define PLATFORM_SYSCALL_TRAP_NO 0x80000000 2778 2779#define ARM64_SYSCALL_CODE_REG_NUM (16) 2780 2781#define ARM64_CLINE_SHIFT 6 2782 2783#if defined(APPLE_ARM64_ARCH_FAMILY) 2784#define L2CERRSTS_DATSBEESV (1ULL << 2) /* L2C data single bit ECC error */ 2785#define L2CERRSTS_DATDBEESV (1ULL << 4) /* L2C data double bit ECC error */ 2786#endif 2787 2788/* 2789 * Timer definitions. 2790 */ 2791#define CNTKCTL_EL1_PL0PTEN (0x1 << 9) /* 1: EL0 access to physical timer regs permitted */ 2792#define CNTKCTL_EL1_PL0VTEN (0x1 << 8) /* 1: EL0 access to virtual timer regs permitted */ 2793#define CNTKCTL_EL1_EVENTI_MASK (0x000000f0) /* Mask for bits describing which bit to use for triggering event stream */ 2794#define CNTKCTL_EL1_EVENTI_SHIFT (0x4) /* Shift for same */ 2795#define CNTKCTL_EL1_EVENTDIR (0x1 << 3) /* 1: one-to-zero transition of specified bit causes event */ 2796#define CNTKCTL_EL1_EVNTEN (0x1 << 2) /* 1: enable event stream */ 2797#define CNTKCTL_EL1_PL0VCTEN (0x1 << 1) /* 1: EL0 access to virtual timebase + frequency reg enabled */ 2798#define CNTKCTL_EL1_PL0PCTEN (0x1 << 0) /* 1: EL0 access to physical timebase + frequency reg enabled */ 2799 2800#define CNTV_CTL_EL0_ISTATUS (0x1 << 2) /* (read only): whether interrupt asserted */ 2801#define CNTV_CTL_EL0_IMASKED (0x1 << 1) /* 1: interrupt masked */ 2802#define CNTV_CTL_EL0_ENABLE (0x1 << 0) /* 1: virtual timer enabled */ 2803 2804#define CNTP_CTL_EL0_ISTATUS CNTV_CTL_EL0_ISTATUS 2805#define CNTP_CTL_EL0_IMASKED CNTV_CTL_EL0_IMASKED 2806#define CNTP_CTL_EL0_ENABLE CNTV_CTL_EL0_ENABLE 2807 2808#define MIDR_EL1_REV_SHIFT 0 2809#define MIDR_EL1_REV_MASK (0xf << MIDR_EL1_REV_SHIFT) 2810#define MIDR_EL1_PNUM_SHIFT 4 2811#define MIDR_EL1_PNUM_MASK (0xfff << MIDR_EL1_PNUM_SHIFT) 2812#define MIDR_EL1_ARCH_SHIFT 16 2813#define MIDR_EL1_ARCH_MASK (0xf << MIDR_EL1_ARCH_SHIFT) 2814#define MIDR_EL1_VAR_SHIFT 20 2815#define MIDR_EL1_VAR_MASK (0xf << MIDR_EL1_VAR_SHIFT) 2816#define MIDR_EL1_IMP_SHIFT 24 2817#define MIDR_EL1_IMP_MASK (0xff << MIDR_EL1_IMP_SHIFT) 2818 2819#define MIDR_FIJI (0x002 << MIDR_EL1_PNUM_SHIFT) 2820#define MIDR_CAPRI (0x003 << MIDR_EL1_PNUM_SHIFT) 2821#define MIDR_MAUI (0x004 << MIDR_EL1_PNUM_SHIFT) 2822#define MIDR_ELBA (0x005 << MIDR_EL1_PNUM_SHIFT) 2823#define MIDR_CAYMAN (0x006 << MIDR_EL1_PNUM_SHIFT) 2824#define MIDR_MYST (0x007 << MIDR_EL1_PNUM_SHIFT) 2825#define MIDR_SKYE_MONSOON (0x008 << MIDR_EL1_PNUM_SHIFT) 2826#define MIDR_SKYE_MISTRAL (0x009 << MIDR_EL1_PNUM_SHIFT) 2827#define MIDR_CYPRUS_VORTEX (0x00B << MIDR_EL1_PNUM_SHIFT) 2828#define MIDR_CYPRUS_TEMPEST (0x00C << MIDR_EL1_PNUM_SHIFT) 2829#define MIDR_M9 (0x00F << MIDR_EL1_PNUM_SHIFT) 2830#define MIDR_ARUBA_VORTEX (0x010 << MIDR_EL1_PNUM_SHIFT) 2831#define MIDR_ARUBA_TEMPEST (0x011 << MIDR_EL1_PNUM_SHIFT) 2832 2833#ifdef APPLELIGHTNING 2834#define MIDR_CEBU_LIGHTNING (0x012 << MIDR_EL1_PNUM_SHIFT) 2835#define MIDR_CEBU_THUNDER (0x013 << MIDR_EL1_PNUM_SHIFT) 2836#define MIDR_TURKS (0x026 << MIDR_EL1_PNUM_SHIFT) 2837#endif 2838 2839#ifdef APPLEFIRESTORM 2840#define MIDR_SICILY_ICESTORM (0x020 << MIDR_EL1_PNUM_SHIFT) 2841#define MIDR_SICILY_FIRESTORM (0x021 << MIDR_EL1_PNUM_SHIFT) 2842#define MIDR_TONGA_ICESTORM (0x022 << MIDR_EL1_PNUM_SHIFT) 2843#define MIDR_TONGA_FIRESTORM (0x023 << MIDR_EL1_PNUM_SHIFT) 2844#define MIDR_JADE_CHOP_ICESTORM (0x024 << MIDR_EL1_PNUM_SHIFT) 2845#define MIDR_JADE_CHOP_FIRESTORM (0x025 << MIDR_EL1_PNUM_SHIFT) 2846#define MIDR_JADE_DIE_ICESTORM (0x028 << MIDR_EL1_PNUM_SHIFT) 2847#define MIDR_JADE_DIE_FIRESTORM (0x029 << MIDR_EL1_PNUM_SHIFT) 2848#endif 2849 2850#ifdef APPLEAVALANCHE 2851#define MIDR_ELLIS_BLIZZARD (0x030 << MIDR_EL1_PNUM_SHIFT) 2852#define MIDR_ELLIS_AVALANCHE (0x031 << MIDR_EL1_PNUM_SHIFT) 2853#endif 2854#define MIDR_STATEN_BLIZZARD (0x032 << MIDR_EL1_PNUM_SHIFT) 2855#define MIDR_STATEN_AVALANCHE (0x033 << MIDR_EL1_PNUM_SHIFT) 2856#define MIDR_RHODES_CHOP_BLIZZARD (0x034 << MIDR_EL1_PNUM_SHIFT) 2857#define MIDR_RHODES_CHOP_AVALANCHE (0x035 << MIDR_EL1_PNUM_SHIFT) 2858#define MIDR_RHODES_DIE_BLIZZARD (0x038 << MIDR_EL1_PNUM_SHIFT) 2859#define MIDR_RHODES_DIE_AVALANCHE (0x039 << MIDR_EL1_PNUM_SHIFT) 2860 2861#if defined(APPLEEVEREST) 2862#define MIDR_CRETE_SAWTOOTH (0x040 << MIDR_EL1_PNUM_SHIFT) 2863#define MIDR_CRETE_EVEREST (0x041 << MIDR_EL1_PNUM_SHIFT) 2864#define MIDR_IBIZA_ACCE (0x042 << MIDR_EL1_PNUM_SHIFT) 2865#define MIDR_IBIZA_ACCP (0x043 << MIDR_EL1_PNUM_SHIFT) 2866#define MIDR_LOBOS_ACCE (0x044 << MIDR_EL1_PNUM_SHIFT) 2867#define MIDR_LOBOS_ACCP (0x045 << MIDR_EL1_PNUM_SHIFT) 2868#define MIDR_CAICOS_ACCE (0x046 << MIDR_EL1_PNUM_SHIFT) 2869#define MIDR_PALMA_ACCE (0x048 << MIDR_EL1_PNUM_SHIFT) 2870#define MIDR_PALMA_ACCP (0x049 << MIDR_EL1_PNUM_SHIFT) 2871#define MIDR_COLL_ACCE (0x050 << MIDR_EL1_PNUM_SHIFT) 2872#define MIDR_COLL_ACCP (0x051 << MIDR_EL1_PNUM_SHIFT) 2873#endif /* defined(APPLEEVEREST) */ 2874 2875/*Donan*/ 2876#define MIDR_DONAN_ACCE (0x052 << MIDR_EL1_PNUM_SHIFT) 2877#define MIDR_DONAN_ACCP (0x053 << MIDR_EL1_PNUM_SHIFT) 2878/*Brava*/ 2879#define MIDR_BRAVA_ACCE (0x054 << MIDR_EL1_PNUM_SHIFT) 2880#define MIDR_BRAVA_ACCP (0x055 << MIDR_EL1_PNUM_SHIFT) 2881 2882 2883 2884 2885/* 2886 * Apple-ISA-Extensions ID Register. 2887 */ 2888#define AIDR_MUL53 (1ULL << 0) 2889#define AIDR_WKDM (1ULL << 1) 2890#define AIDR_ARCHRETENTION (1ULL << 2) 2891 2892 2893 2894 2895/* 2896 * CoreSight debug registers 2897 */ 2898#define CORESIGHT_ED 0 2899#define CORESIGHT_CTI 1 2900#define CORESIGHT_PMU 2 2901#define CORESIGHT_UTT 3 /* Not truly a coresight thing, but at a fixed convenient location right after the coresight region */ 2902 2903#define CORESIGHT_OFFSET(x) ((x) * 0x10000) 2904#define CORESIGHT_REGIONS 4 2905#define CORESIGHT_SIZE 0x1000 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917/* 2918 * ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 2919 * 2920 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2921 * +--------+-------+------+-------+------+-------+-------+------+-------+--------+--------+-------+------+------+-----+------+ 2922 * | rndr | tlb | ts | fhm | dp | sm4 | sm3 | sha3 | rdm | res0 | atomic | crc32 | sha2 | sha1 | aes | res0 | 2923 * +--------+-------+------+-------+------+-------+-------+------+-------+--------+--------+-------+------+------+-----+------+ 2924 */ 2925 2926#define ID_AA64ISAR0_EL1_TS_OFFSET 52 2927#define ID_AA64ISAR0_EL1_TS_MASK (0xfull << ID_AA64ISAR0_EL1_TS_OFFSET) 2928#define ID_AA64ISAR0_EL1_TS_FLAGM_EN (1ull << ID_AA64ISAR0_EL1_TS_OFFSET) 2929#define ID_AA64ISAR0_EL1_TS_FLAGM2_EN (2ull << ID_AA64ISAR0_EL1_TS_OFFSET) 2930 2931#define ID_AA64ISAR0_EL1_FHM_OFFSET 48 2932#define ID_AA64ISAR0_EL1_FHM_MASK (0xfull << ID_AA64ISAR0_EL1_FHM_OFFSET) 2933#define ID_AA64ISAR0_EL1_FHM_8_2 (1ull << ID_AA64ISAR0_EL1_FHM_OFFSET) 2934 2935#define ID_AA64ISAR0_EL1_DP_OFFSET 44 2936#define ID_AA64ISAR0_EL1_DP_MASK (0xfull << ID_AA64ISAR0_EL1_DP_OFFSET) 2937#define ID_AA64ISAR0_EL1_DP_EN (1ull << ID_AA64ISAR0_EL1_DP_OFFSET) 2938 2939#define ID_AA64ISAR0_EL1_SHA3_OFFSET 32 2940#define ID_AA64ISAR0_EL1_SHA3_MASK (0xfull << ID_AA64ISAR0_EL1_SHA3_OFFSET) 2941#define ID_AA64ISAR0_EL1_SHA3_EN (1ull << ID_AA64ISAR0_EL1_SHA3_OFFSET) 2942 2943#define ID_AA64ISAR0_EL1_RDM_OFFSET 28 2944#define ID_AA64ISAR0_EL1_RDM_MASK (0xfull << ID_AA64ISAR0_EL1_RDM_OFFSET) 2945#define ID_AA64ISAR0_EL1_RDM_EN (1ull << ID_AA64ISAR0_EL1_RDM_OFFSET) 2946 2947#define ID_AA64ISAR0_EL1_ATOMIC_OFFSET 20 2948#define ID_AA64ISAR0_EL1_ATOMIC_MASK (0xfull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET) 2949#define ID_AA64ISAR0_EL1_ATOMIC_8_1 (2ull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET) 2950 2951#define ID_AA64ISAR0_EL1_CRC32_OFFSET 16 2952#define ID_AA64ISAR0_EL1_CRC32_MASK (0xfull << ID_AA64ISAR0_EL1_CRC32_OFFSET) 2953#define ID_AA64ISAR0_EL1_CRC32_EN (1ull << ID_AA64ISAR0_EL1_CRC32_OFFSET) 2954 2955#define ID_AA64ISAR0_EL1_SHA2_OFFSET 12 2956#define ID_AA64ISAR0_EL1_SHA2_MASK (0xfull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2957#define ID_AA64ISAR0_EL1_SHA2_EN (1ull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2958#define ID_AA64ISAR0_EL1_SHA2_512_EN (2ull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2959 2960#define ID_AA64ISAR0_EL1_SHA1_OFFSET 8 2961#define ID_AA64ISAR0_EL1_SHA1_MASK (0xfull << ID_AA64ISAR0_EL1_SHA1_OFFSET) 2962#define ID_AA64ISAR0_EL1_SHA1_EN (1ull << ID_AA64ISAR0_EL1_SHA1_OFFSET) 2963 2964#define ID_AA64ISAR0_EL1_AES_OFFSET 4 2965#define ID_AA64ISAR0_EL1_AES_MASK (0xfull << ID_AA64ISAR0_EL1_AES_OFFSET) 2966#define ID_AA64ISAR0_EL1_AES_EN (1ull << ID_AA64ISAR0_EL1_AES_OFFSET) 2967#define ID_AA64ISAR0_EL1_AES_PMULL_EN (2ull << ID_AA64ISAR0_EL1_AES_OFFSET) 2968 2969/* 2970 * ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 1 2971 * 2972 * 63 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2973 * +------+------+-----+------+---------+------+---------+-----+-----+-------+------+-------+-----+-----+-----+ 2974 * | res0 | i8mm | dgh | bf16 | specres | sb | frintts | gpi | gpa | lrcpc | fcma | jscvt | api | apa | dpb | 2975 * +------+------+-----+------+---------+------+---------+-----+-----+-------+------+-------+-----+-----+-----+ 2976 */ 2977 2978#define ID_AA64ISAR1_EL1_I8MM_OFFSET 52 2979#define ID_AA64ISAR1_EL1_I8MM_MASK (0xfull << ID_AA64ISAR1_EL1_I8MM_OFFSET) 2980#define ID_AA64ISAR1_EL1_I8MM_EN (1ull << ID_AA64ISAR1_EL1_I8MM_OFFSET) 2981 2982#define ID_AA64ISAR1_EL1_DGH_OFFSET 48 2983#define ID_AA64ISAR1_EL1_DGH_MASK (0xfull << ID_AA64ISAR1_EL1_DGH_OFFSET) 2984 2985#define ID_AA64ISAR1_EL1_BF16_OFFSET 44 2986#define ID_AA64ISAR1_EL1_BF16_MASK (0xfull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2987#define ID_AA64ISAR1_EL1_BF16_EN (1ull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2988#define ID_AA64ISAR1_EL1_EBF16_EN (2ull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2989 2990#define ID_AA64ISAR1_EL1_SPECRES_OFFSET 40 2991#define ID_AA64ISAR1_EL1_SPECRES_MASK (0xfull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2992#define ID_AA64ISAR1_EL1_SPECRES_EN (1ull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2993#define ID_AA64ISAR1_EL1_SPECRES2_EN (2ull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2994 2995#define ID_AA64ISAR1_EL1_SB_OFFSET 36 2996#define ID_AA64ISAR1_EL1_SB_MASK (0xfull << ID_AA64ISAR1_EL1_SB_OFFSET) 2997#define ID_AA64ISAR1_EL1_SB_EN (1ull << ID_AA64ISAR1_EL1_SB_OFFSET) 2998 2999#define ID_AA64ISAR1_EL1_FRINTTS_OFFSET 32 3000#define ID_AA64ISAR1_EL1_FRINTTS_MASK (0xfull << ID_AA64ISAR1_EL1_FRINTTS_OFFSET) 3001#define ID_AA64ISAR1_EL1_FRINTTS_EN (1ull << ID_AA64ISAR1_EL1_FRINTTS_OFFSET) 3002 3003#define ID_AA64ISAR1_EL1_GPI_OFFSET 28 3004#define ID_AA64ISAR1_EL1_GPI_MASK (0xfull << ID_AA64ISAR1_EL1_GPI_OFFSET) 3005#define ID_AA64ISAR1_EL1_GPI_EN (1ull << ID_AA64ISAR1_EL1_GPI_OFFSET) 3006 3007#define ID_AA64ISAR1_EL1_GPA_OFFSET 24 3008#define ID_AA64ISAR1_EL1_GPA_MASK (0xfull << ID_AA64ISAR1_EL1_GPA_OFFSET) 3009 3010#define ID_AA64ISAR1_EL1_LRCPC_OFFSET 20 3011#define ID_AA64ISAR1_EL1_LRCPC_MASK (0xfull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 3012#define ID_AA64ISAR1_EL1_LRCPC_EN (1ull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 3013#define ID_AA64ISAR1_EL1_LRCP2C_EN (2ull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 3014 3015#define ID_AA64ISAR1_EL1_FCMA_OFFSET 16 3016#define ID_AA64ISAR1_EL1_FCMA_MASK (0xfull << ID_AA64ISAR1_EL1_FCMA_OFFSET) 3017#define ID_AA64ISAR1_EL1_FCMA_EN (1ull << ID_AA64ISAR1_EL1_FCMA_OFFSET) 3018 3019#define ID_AA64ISAR1_EL1_JSCVT_OFFSET 12 3020#define ID_AA64ISAR1_EL1_JSCVT_MASK (0xfull << ID_AA64ISAR1_EL1_JSCVT_OFFSET) 3021#define ID_AA64ISAR1_EL1_JSCVT_EN (1ull << ID_AA64ISAR1_EL1_JSCVT_OFFSET) 3022 3023#define ID_AA64ISAR1_EL1_API_OFFSET 8 3024#define ID_AA64ISAR1_EL1_API_MASK (0xfull << ID_AA64ISAR1_EL1_API_OFFSET) 3025#define ID_AA64ISAR1_EL1_API_PAuth_EN (1ull << ID_AA64ISAR1_EL1_API_OFFSET) 3026#define ID_AA64ISAR1_EL1_API_PAuth2_EN (3ull << ID_AA64ISAR1_EL1_API_OFFSET) 3027#define ID_AA64ISAR1_EL1_API_FPAC_EN (4ull << ID_AA64ISAR1_EL1_API_OFFSET) 3028#define ID_AA64ISAR1_EL1_API_FPACCOMBINE (5ull << ID_AA64ISAR1_EL1_API_OFFSET) 3029 3030#define ID_AA64ISAR1_EL1_APA_OFFSET 4 3031#define ID_AA64ISAR1_EL1_APA_MASK (0xfull << ID_AA64ISAR1_EL1_APA_OFFSET) 3032 3033#define ID_AA64ISAR1_EL1_DPB_OFFSET 0 3034#define ID_AA64ISAR1_EL1_DPB_MASK (0xfull << ID_AA64ISAR1_EL1_DPB_OFFSET) 3035#define ID_AA64ISAR1_EL1_DPB_EN (1ull << ID_AA64ISAR1_EL1_DPB_OFFSET) 3036#define ID_AA64ISAR1_EL1_DPB2_EN (2ull << ID_AA64ISAR1_EL1_DPB_OFFSET) 3037 3038/* 3039 * ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 2 3040 * 3041 * 63 56 55 52 51 24 23 20 19 8 7 4 3 0 3042 * +------+------+------+------+-------+-------+------+ 3043 * | res2 | CSSC | res1 | BC | res0 | RPRES | WFxT | 3044 * +------+------+------+------+-------+-------+------+ 3045 */ 3046 3047 3048#define ID_AA64ISAR2_EL1_CSSC_OFFSET 52 3049#define ID_AA64ISAR2_EL1_CSSC_MASK (0xfull << ID_AA64ISAR2_EL1_CSSC_OFFSET) 3050#define ID_AA64ISAR2_EL1_CSSC_EN (1ull << ID_AA64ISAR2_EL1_CSSC_OFFSET) 3051 3052#define ID_AA64ISAR2_EL1_BC_OFFSET 20 3053#define ID_AA64ISAR2_EL1_BC_MASK (0xfull << ID_AA64ISAR2_EL1_BC_OFFSET) 3054#define ID_AA64ISAR2_EL1_BC_EN (1ull << ID_AA64ISAR2_EL1_BC_OFFSET) 3055 3056#define ID_AA64ISAR2_EL1_RPRES_OFFSET 4 3057#define ID_AA64ISAR2_EL1_RPRES_MASK (0xfull << ID_AA64ISAR2_EL1_RPRES_OFFSET) 3058#define ID_AA64ISAR2_EL1_RPRES_EN (1ull << ID_AA64ISAR2_EL1_RPRES_OFFSET) 3059 3060#define ID_AA64ISAR2_EL1_WFxT_OFFSET 0 3061#define ID_AA64ISAR2_EL1_WFxT_MASK (0xfull << ID_AA64ISAR2_EL1_WFxT_OFFSET) 3062#define ID_AA64ISAR2_EL1_WFxT_EN (1ull << ID_AA64ISAR2_EL1_WFxT_OFFSET) 3063 3064 3065/* 3066 * ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0 3067 * 63 60 59 56 55 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 3068 * +-------+-------+------------+-------+----------+-----------+-----------+--------+---------+---------+-----------+--------+--------+----------+---------+ 3069 * | ECV | FGT | RES0 | ExS | TGran4_2 | TGran64_2 | TGran16_2 | TGran4 | TGran64 | TGran16 | BigEndEL0 | SNSMem | BigEnd | ASIDBits | PARange | 3070 * +-------+-------+------------+-------+----------+-----------+-----------+--------+---------+---------+-----------+--------+--------+----------+---------+ 3071 */ 3072 3073#define ID_AA64MMFR0_EL1_ECV_OFFSET 60 3074#define ID_AA64MMFR0_EL1_ECV_MASK (0xfull << ID_AA64MMFR0_EL1_ECV_OFFSET) 3075#define ID_AA64MMFR0_EL1_ECV_EN (1ull << ID_AA64MMFR0_EL1_ECV_OFFSET) 3076 3077/* 3078 * ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2 3079 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 14 8 7 4 3 0 3080 * +------+-------+-------+-------+--------+-------+-------+------+------+------+-------+---------+------+-------+-------+-------+ 3081 * | E0PD | EVT | BBM | TTL | RES0 | FWB | IDS | AT | ST | NV | CCIDX | VARANGE | IESB | LSM | UAO | CnP | 3082 * +------+-------+-------+-------+--------+-------+-------+------+------+------+-------+---------+------+-------+-------+-------+ 3083 */ 3084 3085#define ID_AA64MMFR2_EL1_AT_OFFSET 32 3086#define ID_AA64MMFR2_EL1_AT_MASK (0xfull << ID_AA64MMFR2_EL1_AT_OFFSET) 3087#define ID_AA64MMFR2_EL1_AT_LSE2_EN (1ull << ID_AA64MMFR2_EL1_AT_OFFSET) 3088#define ID_AA64MMFR2_EL1_VARANGE_OFFSET 16 3089#define ID_AA64MMFR2_EL1_VARANGE_MASK (0xfull << ID_AA64MMFR2_EL1_VARANGE_OFFSET) 3090 3091#define ID_AA64MMFR2_EL1_CNP_OFFSET 0 3092#define ID_AA64MMFR2_EL1_CNP_MASK (0xfull << ID_AA64MMFR2_EL1_CNP_OFFSET) 3093#define ID_AA64MMFR2_EL1_CNP_EN (1ull << ID_AA64MMFR2_EL1_CNP_OFFSET) 3094 3095/* 3096 * ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 3097 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 3098 * +--------+--------+--------+-------+-------+--------+--------+-------+-------+-----+---------+------+-----+-----+-----+-----+ 3099 * | CSV3 | CSV2 | RES0 | DIT | AMU | MPAM | SEL2 | SVE | RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 | 3100 * +--------+--------+--------+-------+-------+--------+--------+-------+-------+-----+---------+------+-----+-----+-----+-----+ 3101 */ 3102 3103#define ID_AA64PFR0_EL1_CSV3_OFFSET 60 3104#define ID_AA64PFR0_EL1_CSV3_MASK (0xfull << ID_AA64PFR0_EL1_CSV3_OFFSET) 3105#define ID_AA64PFR0_EL1_CSV3_EN (1ull << ID_AA64PFR0_EL1_CSV3_OFFSET) 3106 3107#define ID_AA64PFR0_EL1_CSV2_OFFSET 56 3108#define ID_AA64PFR0_EL1_CSV2_MASK (0xfull << ID_AA64PFR0_EL1_CSV2_OFFSET) 3109#define ID_AA64PFR0_EL1_CSV2_EN (1ull << ID_AA64PFR0_EL1_CSV2_OFFSET) 3110#define ID_AA64PFR0_EL1_CSV2_2 (2ull << ID_AA64PFR0_EL1_CSV2_OFFSET) 3111 3112#define ID_AA64PFR0_EL1_DIT_OFFSET 48 3113#define ID_AA64PFR0_EL1_DIT_MASK (0xfull << ID_AA64PFR0_EL1_DIT_OFFSET) 3114#define ID_AA64PFR0_EL1_DIT_EN (1ull << ID_AA64PFR0_EL1_DIT_OFFSET) 3115 3116#define ID_AA64PFR0_EL1_AdvSIMD_OFFSET 20 3117#define ID_AA64PFR0_EL1_AdvSIMD_MASK (0xfull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 3118#define ID_AA64PFR0_EL1_AdvSIMD_HPFPCVT (0x0ull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 3119#define ID_AA64PFR0_EL1_AdvSIMD_FP16 (0x1ull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 3120#define ID_AA64PFR0_EL1_AdvSIMD_DIS (0xfull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 3121 3122/* 3123 * ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1 3124 * 63 20 19 16 15 12 11 8 7 4 3 0 3125 * +----------------------------------+-----------+----------+-------+------+------+ 3126 * | RES0 | MPAM_frac | RAS_frac | MTE | SSBS | BT | 3127 * +----------------------------------+-----------+----------+-------+------+------+ 3128 */ 3129 3130 3131 3132 3133#define ID_AA64PFR1_EL1_SME_OFFSET 24 3134#define ID_AA64PFR1_EL1_SME_MASK (0xfull << ID_AA64PFR1_EL1_SME_OFFSET) 3135#define ID_AA64PFR1_EL1_SME_EN (1ull << ID_AA64PFR1_EL1_SME_OFFSET) 3136#define ID_AA64PFR1_EL1_CSV2_frac_OFFSET 32 3137#define ID_AA64PFR1_EL1_CSV2_frac_MASK (0xfull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 3138#define ID_AA64PFR1_EL1_CSV2_frac_1p1 (1ull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 3139#define ID_AA64PFR1_EL1_CSV2_frac_1p2 (2ull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 3140 3141 3142#define ID_AA64PFR1_EL1_SSBS_OFFSET 4 3143#define ID_AA64PFR1_EL1_SSBS_MASK (0xfull << ID_AA64PFR1_EL1_SSBS_OFFSET) 3144#define ID_AA64PFR1_EL1_SSBS_EN (1ull << ID_AA64PFR1_EL1_SSBS_OFFSET) 3145 3146#define ID_AA64PFR1_EL1_BT_OFFSET 0 3147#define ID_AA64PFR1_EL1_BT_MASK (0xfull << ID_AA64PFR1_EL1_BT_OFFSET) 3148#define ID_AA64PFR1_EL1_BT_EN (1ull << ID_AA64PFR1_EL1_BT_OFFSET) 3149 3150/* 3151 * ID_AA64PFR2_EL1 - AArch64 Processor Feature Register 2 3152 */ 3153 3154 3155 3156 3157 3158/* 3159 * ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1 3160 * 3161 * 63 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 3162 * +------+--------+-----+-----+-----+-----+------+---------+-------+------+------+------+----------+--------+ 3163 * | res0 | nTLBPA | AFP | HCX | ETS | TWED | XNX | SpecSEI | PAN | LO | HPDS | VH | VMIDBits | HAFDBS | 3164 * +------+--------+-----+-----+-----+-----+------+---------+-------+------+------+------+----------+--------+ 3165 */ 3166 3167#define ID_AA64MMFR1_EL1_AFP_OFFSET 44 3168#define ID_AA64MMFR1_EL1_AFP_MASK (0xfull << ID_AA64MMFR1_EL1_AFP_OFFSET) 3169#define ID_AA64MMFR1_EL1_AFP_EN (1ull << ID_AA64MMFR1_EL1_AFP_OFFSET) 3170 3171#define ID_AA64MMFR1_EL1_HCX_OFFSET 40 3172#define ID_AA64MMFR1_EL1_HCX_MASK (0xfull << ID_AA64MMFR1_EL1_HCX_OFFSET) 3173#define ID_AA64MMFR1_EL1_HCX_EN (1ull << ID_AA64MMFR1_EL1_HCX_OFFSET) 3174 3175/* 3176 * ID_AA64SMFR0_EL1 - SME Feature ID Register 0 3177 * 3178 * 63 62 60 59 56 55 52 51 49 48 47 44 43 40 39 36 35 34 33 32 31 0 3179 * +------+------+--------+--------+------+--------+--------+------+-------+--------+--------+---------+--------+------+ 3180 * | FA64 | res0 | SMEver | I16I64 | res0 | F64F64 | I16I32 | res0 | I8I32 | F16F32 | B16F32 | BI32I32 | F32F32 | res0 | 3181 * +------+------+--------+--------+------+--------+--------+------+-------+--------+--------+---------+--------+------+ 3182 */ 3183 3184 3185#define ID_AA64SMFR0_EL1_SMEver_OFFSET 56 3186#define ID_AA64SMFR0_EL1_SMEver_MASK (0xfull << ID_AA64SMFR0_EL1_SMEver_OFFSET) 3187#define ID_AA64SMFR0_EL1_SMEver_SME (0ull << ID_AA64SMFR0_EL1_SMEver_OFFSET) 3188#define ID_AA64SMFR0_EL1_SMEver_SME2 (1ull << ID_AA64SMFR0_EL1_SMEver_OFFSET) 3189 3190#define ID_AA64SMFR0_EL1_I16I64_OFFSET 52 3191#define ID_AA64SMFR0_EL1_I16I64_MASK (0xfull << ID_AA64SMFR0_EL1_I16I64_OFFSET) 3192#define ID_AA64SMFR0_EL1_I16I64_EN (0xfull << ID_AA64SMFR0_EL1_I16I64_OFFSET) 3193 3194#define ID_AA64SMFR0_EL1_F64F64_OFFSET 48 3195#define ID_AA64SMFR0_EL1_F64F64_MASK (1ull << ID_AA64SMFR0_EL1_F64F64_OFFSET) 3196#define ID_AA64SMFR0_EL1_F64F64_EN (1ull << ID_AA64SMFR0_EL1_F64F64_OFFSET) 3197 3198#define ID_AA64SMFR0_EL1_I16I32_OFFSET 44 3199#define ID_AA64SMFR0_EL1_I16I32_MASK (0xfull << ID_AA64SMFR0_EL1_I16I32_OFFSET) 3200#define ID_AA64SMFR0_EL1_I16I32_EN (0x5ull << ID_AA64SMFR0_EL1_I16I32_OFFSET) 3201 3202 3203 3204#define ID_AA64SMFR0_EL1_I8I32_OFFSET 36 3205#define ID_AA64SMFR0_EL1_I8I32_MASK (0xfull << ID_AA64SMFR0_EL1_I8I32_OFFSET) 3206#define ID_AA64SMFR0_EL1_I8I32_EN (0xfull << ID_AA64SMFR0_EL1_I8I32_OFFSET) 3207 3208#define ID_AA64SMFR0_EL1_F16F32_OFFSET 35 3209#define ID_AA64SMFR0_EL1_F16F32_MASK (1ull << ID_AA64SMFR0_EL1_F16F32_OFFSET) 3210#define ID_AA64SMFR0_EL1_F16F32_EN (1ull << ID_AA64SMFR0_EL1_F16F32_OFFSET) 3211 3212#define ID_AA64SMFR0_EL1_B16F32_OFFSET 34 3213#define ID_AA64SMFR0_EL1_B16F32_MASK (1ull << ID_AA64SMFR0_EL1_B16F32_OFFSET) 3214#define ID_AA64SMFR0_EL1_B16F32_EN (1ull << ID_AA64SMFR0_EL1_B16F32_OFFSET) 3215 3216#define ID_AA64SMFR0_EL1_BI32I32_OFFSET 33 3217#define ID_AA64SMFR0_EL1_BI32I32_MASK (1ull << ID_AA64SMFR0_EL1_BI32I32_OFFSET) 3218#define ID_AA64SMFR0_EL1_BI32I32_EN (1ull << ID_AA64SMFR0_EL1_BI32I32_OFFSET) 3219 3220#define ID_AA64SMFR0_EL1_F32F32_OFFSET 32 3221#define ID_AA64SMFR0_EL1_F32F32_MASK (1ull << ID_AA64SMFR0_EL1_F32F32_OFFSET) 3222#define ID_AA64SMFR0_EL1_F32F32_EN (1ull << ID_AA64SMFR0_EL1_F32F32_OFFSET) 3223 3224 3225 3226 3227#define APSTATE_G_SHIFT (0) 3228#define APSTATE_P_SHIFT (1) 3229#define APSTATE_A_SHIFT (2) 3230#define APSTATE_AP_MASK ((1ULL << APSTATE_A_SHIFT) | (1ULL << APSTATE_P_SHIFT)) 3231 3232 3233#define ACTLR_EL1_EnTSO (1ULL << 1) 3234#define ACTLR_EL1_EnAPFLG (1ULL << 4) 3235#define ACTLR_EL1_EnAFP (1ULL << 5) 3236#define ACTLR_EL1_EnPRSV (1ULL << 6) 3237 3238 3239#if HAS_USAT_BIT 3240#define ACTLR_EL1_USAT_OFFSET 0 3241#define ACTLR_EL1_USAT_MASK (1ULL << ACTLR_EL1_USAT_OFFSET) 3242#define ACTLR_EL1_USAT ACTLR_EL1_USAT_MASK 3243#endif 3244 3245 3246 3247 3248 3249 3250#ifdef HAS_DISDDHWP0 3251#define ACTLR_EL1_DisDDHWP0_OFFSET 17 3252#define ACTLR_EL1_DisDDHWP0_MASK (1ULL << ACTLR_EL1_DisDDHWP0_OFFSET) 3253#define ACTLR_EL1_DisDDHWP0 ACTLR_EL1_DisDDHWP0_MASK 3254#endif /* HAS_DISDDDHWP0 */ 3255 3256 3257#if defined(HAS_APPLE_PAC) 3258// The value of ptrauth_string_discriminator("recover"), hardcoded so it can be used from assembly code 3259#define PAC_DISCRIMINATOR_RECOVER 0x1e02 3260#endif 3261 3262 3263#define CTR_EL0_L1Ip_OFFSET 14 3264#define CTR_EL0_L1Ip_VIPT (2ULL << CTR_EL0_L1Ip_OFFSET) 3265#define CTR_EL0_L1Ip_PIPT (3ULL << CTR_EL0_L1Ip_OFFSET) 3266#define CTR_EL0_L1Ip_MASK (3ULL << CTR_EL0_L1Ip_OFFSET) 3267 3268 3269#define ACNTHV_CTL_EL2 S3_1_C15_C7_4 3270#define ACNTHV_CTL_EL2_EN_OFFSET 0 3271#define ACNTHV_CTL_EL2_EN_MASK (1ULL << ACNTHV_CTL_EL2_EN_OFFSET) 3272 3273#ifdef __ASSEMBLER__ 3274 3275/* 3276 * Conditionally write to system/special-purpose register. 3277 * The register is written to only when the first two arguments 3278 * do not match. If they do match, the macro jumps to a 3279 * caller-provided label. 3280 * The _ISB variant also conditionally issues an ISB after the MSR. 3281 * 3282 * $0 - System/special-purpose register to modify 3283 * $1 - Register containing current FPCR value 3284 * $2 - Register containing expected value 3285 * $3 - Label to jump to when register is already set to expected value 3286 */ 3287.macro CMSR 3288cmp $1, $2 3289 3290/* Skip expensive MSR if not required */ 3291b.eq $3f 3292msr $0, $2 3293.endmacro 3294 3295.macro CMSR_ISB 3296CMSR $0, $1, $2, $3 3297isb sy 3298.endmacro 3299 3300/* 3301 * Modify FPCR only if it does not contain the XNU default value. 3302 * $0 - Register containing current FPCR value 3303 * $1 - Scratch register 3304 * $2 - Label to jump to when FPCR is already set to default value 3305 */ 3306.macro SANITIZE_FPCR 3307mov $1, #FPCR_DEFAULT 3308CMSR FPCR, $0, $1, $2 3309.endmacro 3310 3311/* 3312 * Family of macros that can be used to protect code sections such that they 3313 * are only executed on a particular SoC/Revision/CPU, and skipped otherwise. 3314 * All macros will forward-jump to 1f when the condition is not matched. 3315 * This label may be defined manually, or implicitly through the use of 3316 * the EXEC_END macro. 3317 * For cores, XX can be: EQ (equal), ALL (don't care). 3318 * For revisions, XX can be: EQ (equal), LO (lower than), HS (higher or same), ALL (don't care). 3319 */ 3320 3321/* 3322 * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX 3323 * $1 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 3324 * $2 - GPR containing MIDR_EL1 value 3325 * $3 - Scratch register 3326 */ 3327.macro EXEC_COREEQ_REVEQ 3328and $3, $2, #MIDR_EL1_PNUM_MASK 3329cmp $3, $0 3330b.ne 1f 3331 3332mov $3, $2 3333bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 3334ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 3335cmp $3, $1 3336b.ne 1f 3337.endmacro 3338 3339.macro EXEC_COREEQ_REVLO 3340and $3, $2, #MIDR_EL1_PNUM_MASK 3341cmp $3, $0 3342b.ne 1f 3343 3344mov $3, $2 3345bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 3346ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 3347cmp $3, $1 3348b.pl 1f 3349.endmacro 3350 3351.macro EXEC_COREEQ_REVHS 3352and $3, $2, #MIDR_EL1_PNUM_MASK 3353cmp $3, $0 3354b.ne 1f 3355 3356mov $3, $2 3357bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 3358ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 3359cmp $3, $1 3360b.mi 1f 3361.endmacro 3362 3363/* 3364 * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 3365 * $1 - GPR containing MIDR_EL1 value 3366 * $2 - Scratch register 3367 */ 3368.macro EXEC_COREALL_REVEQ 3369mov $2, $1 3370bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3371ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3372cmp $2, $0 3373b.ne 1f 3374.endmacro 3375 3376.macro EXEC_COREALL_REVLO 3377mov $2, $1 3378bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3379ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3380cmp $2, $0 3381b.pl 1f 3382.endmacro 3383 3384.macro EXEC_COREALL_REVHS 3385mov $2, $1 3386bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3387ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3388cmp $2, $0 3389b.mi 1f 3390.endmacro 3391 3392.macro CMP_FOREACH reg, cc, label, car, cdr:vararg 3393 cmp \reg, \car 3394 b.\cc \label 3395.ifnb \cdr 3396 CMP_FOREACH \reg, \cc, \label, \cdr 3397.endif 3398.endm 3399 3400.macro EXEC_COREIN_REVALL midr_el1, scratch, midr_list:vararg 3401and \scratch, \midr_el1, #MIDR_EL1_PNUM_MASK 3402 CMP_FOREACH \scratch, eq, Lmatch\@, \midr_list 3403 b 1f 3404Lmatch\@: 3405.endm 3406 3407/* 3408 * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX 3409 * $1 - GPR containing MIDR_EL1 value 3410 * $2 - Scratch register 3411 */ 3412.macro EXEC_COREEQ_REVALL 3413and $2, $1, #MIDR_EL1_PNUM_MASK 3414cmp $2, $0 3415 b.ne 1f 3416.endmacro 3417 3418/* 3419 * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 3420 * $1 - GPR containing MIDR_EL1 value 3421 * $2 - Scratch register 3422 */ 3423.macro EXEC_PCORE_REVEQ 3424ARM64_IS_PCORE $2 3425cbz $2, 1f 3426 3427mov $2, $1 3428bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3429ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3430cmp $2, $0 3431b.ne 1f 3432.endmacro 3433 3434.macro EXEC_PCORE_REVLO 3435ARM64_IS_PCORE $2 3436cbz $2, 1f 3437 3438mov $2, $1 3439bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3440ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3441cmp $2, $0 3442b.pl 1f 3443.endmacro 3444 3445.macro EXEC_PCORE_REVHS 3446ARM64_IS_PCORE $2 3447cbz $2, 1f 3448 3449mov $2, $1 3450bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3451ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3452cmp $2, $0 3453b.mi 1f 3454.endmacro 3455 3456.macro EXEC_ECORE_REVEQ 3457ARM64_IS_ECORE $2 3458cbz $2, 1f 3459 3460mov $2, $1 3461bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3462ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3463cmp $2, $0 3464b.ne 1f 3465.endmacro 3466 3467.macro EXEC_ECORE_REVLO 3468ARM64_IS_ECORE $2 3469cbz $2, 1f 3470 3471mov $2, $1 3472bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3473ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3474cmp $2, $0 3475b.pl 1f 3476.endmacro 3477 3478.macro EXEC_ECORE_REVHS 3479ARM64_IS_ECORE $2 3480cbz $2, 1f 3481 3482mov $2, $1 3483bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 3484ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 3485cmp $2, $0 3486b.mi 1f 3487.endmacro 3488 3489/* 3490 * $0 - GPR containing MIDR_EL1 value 3491 * $1 - Scratch register 3492 */ 3493.macro EXEC_PCORE_REVALL 3494ARM64_IS_PCORE $1 3495cbz $1, 1f 3496.endmacro 3497 3498.macro EXEC_ECORE_REVALL 3499ARM64_IS_ECORE $1 3500cbz $1, 1f 3501.endmacro 3502 3503/* 3504 * Macro that defines the label that all EXEC_COREXX_REVXX macros jump to. 3505 */ 3506.macro EXEC_END 35071: 3508.endmacro 3509 3510/* 3511 * Wedges CPUs with a specified core that are below a specified revision. This 3512 * macro is intended for CPUs that have been deprecated in iBoot and may have 3513 * incorrect behavior if they continue running xnu. 3514 */ 3515.macro DEPRECATE_COREEQ_REVLO core, rev, midr_el1, scratch 3516EXEC_COREEQ_REVLO \core, \rev, \midr_el1, \scratch 3517/* BEGIN IGNORE CODESTYLE */ 3518b . 3519/* END IGNORE CODESTYLE */ 3520EXEC_END 3521.endmacro 3522 3523/* 3524 * Sets bits in an SPR register. 3525 * arg0: Name of the register to be accessed. 3526 * arg1: Mask of bits to be set. 3527 * arg2: Scratch register 3528 */ 3529.macro HID_SET_BITS 3530mrs $2, $0 3531orr $2, $2, $1 3532msr $0, $2 3533.endmacro 3534 3535/* 3536 * Clears bits in an SPR register. 3537 * arg0: Name of the register to be accessed. 3538 * arg1: Mask of bits to be cleared. 3539 * arg2: Scratch register 3540 */ 3541.macro HID_CLEAR_BITS 3542mrs $2, $0 3543bic $2, $2, $1 3544msr $0, $2 3545.endmacro 3546 3547/* 3548 * Combines the functionality of HID_CLEAR_BITS followed by HID_SET_BITS into 3549 * a single read-modify-write sequence. 3550 * arg0: Name of the register to be accessed. 3551 * arg1: Mask of bits to be cleared. 3552 * arg2: Value to insert 3553 * arg3: Scratch register 3554 */ 3555.macro HID_INSERT_BITS 3556mrs $3, $0 3557bic $3, $3, $1 3558orr $3, $3, $2 3559msr $0, $3 3560.endmacro 3561 3562/* 3563 * Replaces the value of a field in an implementation-defined system register. 3564 * sreg: system register name 3565 * field: field name within the sysreg, where the assembler symbols 3566 * ARM64_REG_<field>_{shift,width} specify the bounds of the field 3567 * (note that preprocessor macros will not work here) 3568 * value: the value to insert 3569 * scr{1,2}: scratch regs 3570 */ 3571.macro HID_WRITE_FIELD sreg, field, val, scr1, scr2 3572mrs \scr1, \sreg 3573mov \scr2, \val 3574bfi \scr1, \scr2, ARM64_REG_\sreg\()_\field\()_shift, ARM64_REG_\sreg\()_\field\()_width 3575msr \sreg, \scr1 3576.endmacro 3577 3578/* 3579 * This macro is a replacement for ERET with better security properties. 3580 * 3581 * It prevents "straight-line speculation" (an Arm term) past the ERET. 3582 */ 3583.macro ERET_NO_STRAIGHT_LINE_SPECULATION 3584eret 3585#if __ARM_SB_AVAILABLE__ 3586sb // Technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures 3587#else /* __ARM_SB_AVAILABLE__ */ 3588isb // ISB technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures 3589nop // Sequence of six NOPs to pad out and terminate instruction decode group */ 3590nop 3591nop 3592nop 3593nop 3594nop 3595#endif /* !__ARM_SB_AVAILABLE__ */ 3596.endmacro 3597 3598 3599#endif /* __ASSEMBLER__ */ 3600 3601#define MSR(reg, src) __asm__ volatile ("msr " reg ", %0" :: "r" (src)) 3602#define MRS(dest, reg) __asm__ volatile ("mrs %0, " reg : "=r" (dest)) 3603 3604#if XNU_MONITOR 3605#define __ARM_PTE_PHYSMAP__ 1 3606#define PPL_STATE_KERNEL 0 3607#define PPL_STATE_DISPATCH 1 3608#define PPL_STATE_PANIC 2 3609#define PPL_STATE_EXCEPTION 3 3610#endif 3611 3612 3613#if HAS_ESB 3614#define DISR_A_SHIFT 31 3615#define DISR_A (1ULL << DISR_A_SHIFT) 3616#endif 3617#endif /* _ARM64_PROC_REG_H_ */