Processor and exception-syndrome registers (arm64) — implementation sources

PSR64_NZCV_SHIFT source macro

64-bit Program Status Register (PSR64) 31 27 23 22 21 20 19 10 9 5 4 0 +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+ |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0| M | +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+ where: NZCV: Comparison flags PAN: Privileged Access Never SS: Single step IL: Illegal state DAIF: Interrupt masks M: Mode field

#define PSR64_NZCV_SHIFT 28

PSR64_NZCV_WIDTH source macro

64-bit Program Status Register (PSR64) 31 27 23 22 21 20 19 10 9 5 4 0 +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+ |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0| M | +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+ where: NZCV: Comparison flags PAN: Privileged Access Never SS: Single step IL: Illegal state DAIF: Interrupt masks M: Mode field

#define PSR64_NZCV_WIDTH 4

PSR64_NZCV_MASK source macro

64-bit Program Status Register (PSR64) 31 27 23 22 21 20 19 10 9 5 4 0 +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+ |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0| M | +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+ where: NZCV: Comparison flags PAN: Privileged Access Never SS: Single step IL: Illegal state DAIF: Interrupt masks M: Mode field

#define PSR64_NZCV_MASK (0xF << PSR64_NZCV_SHIFT)

PSR64_N_SHIFT source macro

#define PSR64_N_SHIFT 31

PSR64_N source macro

#define PSR64_N (1 << PSR64_N_SHIFT)

PSR64_Z_SHIFT source macro

#define PSR64_Z_SHIFT 30

PSR64_Z source macro

#define PSR64_Z (1 << PSR64_Z_SHIFT)

PSR64_C_SHIFT source macro

#define PSR64_C_SHIFT 29

PSR64_C source macro

#define PSR64_C (1 << PSR64_C_SHIFT)

PSR64_V_SHIFT source macro

#define PSR64_V_SHIFT 28

PSR64_V source macro

#define PSR64_V (1 << PSR64_V_SHIFT)

PSR64_TCO_SHIFT source macro

#define PSR64_TCO_SHIFT 25

PSR64_TCO source macro

#define PSR64_TCO (1 << PSR64_TCO_SHIFT)

PSR64_DIT_SHIFT source macro

#define PSR64_DIT_SHIFT 24

PSR64_DIT source macro

#define PSR64_DIT (1 << PSR64_DIT_SHIFT)

PSR64_UAO_SHIFT source macro

#define PSR64_UAO_SHIFT 23

PSR64_UAO source macro

#define PSR64_UAO (1 << PSR64_UAO_SHIFT)

PSR64_PAN_SHIFT source macro

#define PSR64_PAN_SHIFT 22

PSR64_PAN source macro

#define PSR64_PAN (1 << PSR64_PAN_SHIFT)

PSR64_SS_SHIFT source macro

#define PSR64_SS_SHIFT 21

PSR64_SS source macro

#define PSR64_SS (1 << PSR64_SS_SHIFT)

PSR64_IL_SHIFT source macro

#define PSR64_IL_SHIFT 20

PSR64_IL source macro

#define PSR64_IL (1 << PSR64_IL_SHIFT)

PSR64_SSBS_SHIFT_32 source macro

SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR I do not want to talk about it!

#define PSR64_SSBS_SHIFT_32 23

PSR64_SSBS_SHIFT_64 source macro

SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR I do not want to talk about it!

#define PSR64_SSBS_SHIFT_64 12

PSR64_SSBS_32 source macro

SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR I do not want to talk about it!

#define PSR64_SSBS_32 (1 << PSR64_SSBS_SHIFT_32)

PSR64_SSBS_64 source macro

SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR I do not want to talk about it!

#define PSR64_SSBS_64 (1 << PSR64_SSBS_SHIFT_64)

DAIF_DEBUG_SHIFT source macro

msr DAIF, Xn and mrs Xn, DAIF transfer into and out of bits 9:6

#define DAIF_DEBUG_SHIFT 9

DAIF_DEBUGF source macro

msr DAIF, Xn and mrs Xn, DAIF transfer into and out of bits 9:6

#define DAIF_DEBUGF (1 << DAIF_DEBUG_SHIFT)

DAIF_ASYNC_SHIFT source macro

msr DAIF, Xn and mrs Xn, DAIF transfer into and out of bits 9:6

#define DAIF_ASYNC_SHIFT 8

DAIF_ASYNCF source macro

#define DAIF_ASYNCF (1 << DAIF_ASYNC_SHIFT)

DAIF_IRQF_SHIFT source macro

#define DAIF_IRQF_SHIFT 7

DAIF_IRQF source macro

#define DAIF_IRQF (1 << DAIF_IRQF_SHIFT)

DAIF_FIQF_SHIFT source macro

#define DAIF_FIQF_SHIFT 6

DAIF_FIQF source macro

#define DAIF_FIQF (1 << DAIF_FIQF_SHIFT)

DAIF_ALL source macro

#define DAIF_ALL (DAIF_DEBUGF | DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF)

DAIF_STANDARD_DISABLE source macro

#define DAIF_STANDARD_DISABLE (DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF)

SPSR_INTERRUPTS_ENABLED source macro

#define SPSR_INTERRUPTS_ENABLED(x) (!(x & DAIF_FIQF))

PSR64_SSBS_U32_DEFAULT source macro

#define PSR64_SSBS_U32_DEFAULT PSR64_SSBS_32

PSR64_SSBS_U64_DEFAULT source macro

#define PSR64_SSBS_U64_DEFAULT PSR64_SSBS_64

PSR64_SSBS_KRN_DEFAULT source macro

#define PSR64_SSBS_KRN_DEFAULT PSR64_SSBS_64

PSR64_SSBS_U32_DEFAULT source macro

#define PSR64_SSBS_U32_DEFAULT (0)

PSR64_SSBS_U64_DEFAULT source macro

#define PSR64_SSBS_U64_DEFAULT (0)

PSR64_SSBS_KRN_DEFAULT source macro

#define PSR64_SSBS_KRN_DEFAULT (0)

PSR64_CF source macro

ARM64_TODO: unify with ARM?

#define PSR64_CF 0x20000000

PSR64_MODE_MASK source macro

Carry/Borrow/Extend

#define PSR64_MODE_MASK 0x1F

PSR64_USER_MASK source macro

Carry/Borrow/Extend

#define PSR64_USER_MASK PSR64_NZCV_MASK

PSR64_MODE_USER32_THUMB source macro

#define PSR64_MODE_USER32_THUMB 0x20

PSR64_MODE_RW_SHIFT source macro

#define PSR64_MODE_RW_SHIFT 4

PSR64_MODE_RW_64 source macro

#define PSR64_MODE_RW_64 0

PSR64_MODE_RW_32 source macro

#define PSR64_MODE_RW_32 (0x1 << PSR64_MODE_RW_SHIFT)

PSR64_MODE_EL_SHIFT source macro

#define PSR64_MODE_EL_SHIFT 2

PSR64_MODE_EL_MASK source macro

#define PSR64_MODE_EL_MASK (0x3 << PSR64_MODE_EL_SHIFT)

PSR64_MODE_EL3 source macro

#define PSR64_MODE_EL3 (0x3 << PSR64_MODE_EL_SHIFT)

PSR64_MODE_EL2 source macro

#define PSR64_MODE_EL2 (0x2 << PSR64_MODE_EL_SHIFT)

PSR64_MODE_EL1 source macro

#define PSR64_MODE_EL1 (0x1 << PSR64_MODE_EL_SHIFT)

PSR64_MODE_EL0 source macro

#define PSR64_MODE_EL0 0

PSR64_MODE_EL_KERNEL source macro

#define PSR64_MODE_EL_KERNEL (PSR64_MODE_EL1)

PSR64_MODE_SPX source macro

#define PSR64_MODE_SPX 0x1

PSR64_MODE_SP0 source macro

#define PSR64_MODE_SP0 0

PSR64_USER32_DEFAULT source macro

#define PSR64_USER32_DEFAULT (PSR64_MODE_RW_32 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U32_DEFAULT)

PSR64_USER64_DEFAULT source macro

#define PSR64_USER64_DEFAULT (PSR64_MODE_RW_64 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U64_DEFAULT)

PSR64_KERNEL_STANDARD source macro

#define PSR64_KERNEL_STANDARD (DAIF_STANDARD_DISABLE | PSR64_MODE_RW_64 | PSR64_MODE_EL1 | PSR64_MODE_SP0 | PSR64_SSBS_KRN_DEFAULT)

PSR64_KERNEL_DEFAULT source macro

#define PSR64_KERNEL_DEFAULT (PSR64_KERNEL_STANDARD | PSR64_PAN)

PSR64_KERNEL_DEFAULT source macro

#define PSR64_KERNEL_DEFAULT PSR64_KERNEL_STANDARD

PSR64_IS_KERNEL source macro

#define PSR64_IS_KERNEL(x) ((x & PSR64_MODE_EL_MASK) > PSR64_MODE_EL0)

PSR64_IS_USER source macro

#define PSR64_IS_USER(x) ((x & PSR64_MODE_EL_MASK) == PSR64_MODE_EL0)

PSR64_IS_USER32 source macro

#define PSR64_IS_USER32(x) (PSR64_IS_USER(x) && (x & PSR64_MODE_RW_32))

PSR64_IS_USER64 source macro

#define PSR64_IS_USER64(x) (PSR64_IS_USER(x) && !(x & PSR64_MODE_RW_32))

ESR_EC_SHIFT source macro

Exception Syndrome Register 63 56 55 32 31 26 25 24 0 +------+------+------+--+------------------+ | RES0 | ISS2 | EC |IL| ISS | +------+------+------+--+------------------+ RES0 - Reserved bits. ISS2 - Instruction Specific Syndrome 2. EC - Exception Class IL - Instruction Length ISS - Instruction Specific Syndrome Note: The ISS can have many forms. These are defined separately below.

#define ESR_EC_SHIFT 26

ESR_EC_WIDTH source macro

Exception Syndrome Register 63 56 55 32 31 26 25 24 0 +------+------+------+--+------------------+ | RES0 | ISS2 | EC |IL| ISS | +------+------+------+--+------------------+ RES0 - Reserved bits. ISS2 - Instruction Specific Syndrome 2. EC - Exception Class IL - Instruction Length ISS - Instruction Specific Syndrome Note: The ISS can have many forms. These are defined separately below.

#define ESR_EC_WIDTH 6

ESR_EC_MASK source macro

Exception Syndrome Register 63 56 55 32 31 26 25 24 0 +------+------+------+--+------------------+ | RES0 | ISS2 | EC |IL| ISS | +------+------+------+--+------------------+ RES0 - Reserved bits. ISS2 - Instruction Specific Syndrome 2. EC - Exception Class IL - Instruction Length ISS - Instruction Specific Syndrome Note: The ISS can have many forms. These are defined separately below.

#define ESR_EC_MASK (0x3FULL << ESR_EC_SHIFT)

ESR_EC source macro

#define ESR_EC(x) ((x & ESR_EC_MASK) >> ESR_EC_SHIFT)

ESR_IL_SHIFT source macro

#define ESR_IL_SHIFT 25

ESR_IL source macro

#define ESR_IL (1 << ESR_IL_SHIFT)

ESR_INSTR_IS_2BYTES source macro

#define ESR_INSTR_IS_2BYTES(x) (!(x & ESR_IL))

ESR_ISS_MASK source macro

#define ESR_ISS_MASK 0x01FFFFFF

ESR_ISS source macro

#define ESR_ISS(x) (x & ESR_ISS_MASK)

ESR_EC_UNCATEGORIZED source macro

Define only the classes we need to test in the exception vectors.

#define ESR_EC_UNCATEGORIZED 0x00

ESR_EC_BTI_FAIL source macro

Define only the classes we need to test in the exception vectors.

#define ESR_EC_BTI_FAIL 0x0D

ESR_EC_SVC_64 source macro

Define only the classes we need to test in the exception vectors.

#define ESR_EC_SVC_64 0x15

ESR_EC_HVC_64 source macro

Define only the classes we need to test in the exception vectors.

#define ESR_EC_HVC_64 0x16

ESR_EC_PAC_FAIL source macro

#define ESR_EC_PAC_FAIL 0x1C

ESR_EC_IABORT_EL1 source macro

#define ESR_EC_IABORT_EL1 0x21

ESR_EC_DABORT_EL1 source macro

#define ESR_EC_DABORT_EL1 0x25

ESR_EC_SP_ALIGN source macro

#define ESR_EC_SP_ALIGN 0x26

ESR_EC_BRK_AARCH64 source macro

#define ESR_EC_BRK_AARCH64 0x3C